MACH 5 CPLD Family

Publication#

20446

Rev:

Amendment/

Issue Date:

September 2000

MACH

5 CPLD Family

Fifth Generation MACH Architecture

FEATURES

High logic densities and I/Os for increased logic integration

— 128 to 512 macrocell densities

— 68 to 256 I/Os

Wide selection of density and I/O combinations to support most application needs

— 6 macrocell density options

— 7 I/O options

— Up to 4 I/O options per macrocell density

— Up to 5 density & I/O options for each package

Performance features to ﬁt system needs

— 5.5 ns t

Commercial, 7.5 ns t

Industrial

— 182 MHz f

CNT

— Four programmable power/speed settings per block

Flexible architecture facilitates logic design

— Multiple levels of switch matrices allow for performance-based routing

— 100% routability and pin-out retention

— Synchronous and asynchronous clocking, including dual-edge clocking

— Asynchronous product- or sum-term set or reset

— 16 to 64 output enables

— Functions of up to 32 product terms

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— IEEE 1149.1 compliant for boundary scan testing

— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port

— PCI compliant (-5/-6/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system design

— Bus-Friendly™ Inputs & I/Os

— Individual output slew rate control

— Hot socketing

— Programmable security bit

Advanced E

CMOS process provides high performance, cost effective solutions

Supported by ispDesignEXPERT™ software for rapid logic development

— Supports HDL design methodologies with results optimized for MACH 5 devices

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice and Third-party hardware programming support

— LatticePRO™ software for in-system programmability support on PCs and Automated Test

Equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

and System General

MACH 5 Family

Note:

1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.

2. Preliminary speciﬁcations for new 6.5ns (Tpd) speed grade. 7.5ns speed grade in production now.

GENERAL DESCRIPTION

The MACH

5 family consists of a broad range of high-density and high-I/O Complex

Programmable Logic Devices (CPLDs). The ﬁfth-generation MACH architecture yields fast speeds

at high CPLD densities, low power, and supports additional features such as in-system

programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH

5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.

Manufactured in state-of-the-art ISO 9000 qualiﬁed fabrication facilities on E

CMOS process

technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The

5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the

PCI Local Bus Speciﬁcation

Table 1. MACH 5 Device Features

Feature

M5-128/1

M5LV-128

M5-192/1

M5-256/1

M5LV-256

M5-320

M5LV-320

M5-384

M5LV-384

M5-512

M5LV-512

Supply Voltage (V)

3.3

Macrocells

128

192

256

320

384

512

Maximum User I/O Pins

120

160

192

160

192

256

(ns)

5.5

5.5 5.5 5.5

5.5

6.5

(ns)

3.0

COS

(ns)

4.5

5.0

CNT

(MHz)

182

167

Typical Static Power (mA)

100

IEEE 1149.1 Boundary Scan Compliant

Yes

PCI-Compliant

Yes

MACH 5 Family

Note:

1. C = Commercial grade, I = Industrial grade

2. /1 version recommended for new designs

3. Preliminary speciﬁcatons

With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512

macrocells to support full system logic integration. Extensive routing resources ensure pinout

retention as well as high utilization. It is ideal for PAL

block device integration and a wide range

of other applications including high-speed computing, low-power applications, communications,

and embedded control. At each macrocell density point, Lattice offers several I/O and package

options to meet a wide range of design needs (Table 3).

Note:

1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.

Table 2. MACH 5 Speed Grades

Device

Speed Grade

-5

-6

-7

-10

-12

-15

-20

M5-128

C, I

M5-128/1

C, I

M5LV-128

C,I

C, I

M5-192/1

C, I

M5-256

C, I

M5-256/1

C, I

M5LV-256

C, I

M5-320

C, I

M5LV-320

C, I

M5-384

C, I

M5LV-384

C, I

M5-512

C, I

M5LV-512

C, I

Table 3. MACH 5 Package and I/O Options

M5-128/1

M5LV-128

M5-192/1

M5-256/1

M5LV-256

M5-320

M5LV-320

M5-384

M5LV-384

M5-512

M5LV-512

Supply Voltage

3.3

100-pin TQFP

68, 74

68*, 74

100-pin PQFP

68*

144-pin TQFP

104

144-pin PQFP

104

104*

160-pin PQFP

120

120*

120

120*

120

120*

120

208-pin PQFP

160

240-pin PQFP

184*

256-ball BGA

192

192*

352-ball BGA

256

MACH 5 Family

Advanced power management options allow designers to incrementally reduce power while

maintaining the level of performance needed for today’s complex designs. I/O safety features

allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system

programmable through an IEEE 1149.1 Test Access Port (TAP) interface.

FUNCTIONAL DESCRIPTION

The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The

block

interconnect

provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the

block interconnect is called a

segment

. The second level of interconnect, the

segment

interconnect

, ties all of the segments together. The only logic difference between any two MACH

5 devices is the number of segments. Therefore, once a designer is familiar with one device,

consistent performance can be expected across the entire family. All devices have four clock pins

available which can also be used as logic inputs.

The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block

resembles an independent PAL device, it has superior control and logic generation capabilities.

I/O cells

Product-term array and Logic Allocator

Macrocells

Output enable generator

I/O Cells

The I/Os associated with each PAL block have a path directly back to that PAL block called

local

feedback

. If the I/O is used in another PAL block, the

interconnect feeder

assigns a

block interconnect

line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment

interconnects provide connections between any two signals in a device. The

block feeder

assigns

block interconnect lines and local feedback lines to the PAL block inputs.

Block Interconnect

CLK

Block:

16 MCs

Segment:

4 Blocks

Segment Interconnect

20446G-001

Figure 1. MACH 5 Block Diagram

MACH 5 Family

Product-Term Array and Logic Allocator

The product-term array uses the same sum-of-products architecture as PAL devices and consists of

32 inputs (plus their complements) and 64 product terms arranged in 16

clusters

. A cluster is a sum-

of-products function with either 3 of 4 product terms.

Logic allocators

assign the clusters to macrocells. Each macrocell can accept up to eight clusters of

three or four product terms, but a given cluster can only be steered to one macrocell (Table 4). If

only three product terms in a cluster are steered, the fourth can be used as an input to an XOR

gate for separate logic generation and/or polarity control.

The

wide logic allocator

is comprised of all 16 of the individual logic allocators and acts as an output

switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic

allocation scheme in the MACH 5 device allows for the implementation of large equations (up to

32 product terms) with only one pass through the logic array.

Table 4. Product Term Steering Options for PT Clusters and Macrocells

Macrocell

Available Clusters

Macrocell

Available Clusters

, C

Block Interconnect

Interconnect Feeder

Block

Feeder

I/Os

Macrocells

Logic Alocator

Control Generator

OE Generator

Product-term

Array

Input Register

Path

Local Feedback

20446G-002

Figure 2. PAL Block Structure

MACH 5 Family

Macrocells

The macrocells for MACH 5 devices consist of a storage element which can be conﬁgured for

combinatorial, registered or latched operation (Figure 3). The D-type ﬂip-ﬂops can be conﬁgured

as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell.

Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In

order to use this option, these macrocells must be accessed via the I/O pins associated with

macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it cannot be used

for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The

I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins

for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be

used as “buried” macrocells to drive device logic via the matrix.

Control Generator

The control generator provides four conﬁgurable clock lines and three conﬁgurable set/reset lines to

each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can

be independently selected by any ﬂip-ﬂop within a block. The clock lines can be conﬁgured to

provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks,

and latch enables (Figure 4). Three of the four global clocks, as well as two product-term clocks

and one sum-term clock, are available per PAL block. Positive or negative edge clocking is

available as well as advanced clocking features such as

complementary and biphase clocking.

Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful

in applications such as fast data paths. A biphase clock line clocks ﬂip-ﬂops on both the positive

and negative edges of the clock. The conﬁguration options for the four clock lines per PAL block

are as follows:

Clock Line 0 Options

Global clock (0, 1, 2, or 3) with positive or negative edge clock enable

Product-term clock (A*B*C)

Sum-term clock (A+B+C)

Logic

Allocator

5-8

Clusters/

Prog. Polarity

Mode