Publication#
ISPM4A
Rev:
D
Amendment/
0
Issue Date:
August 2000
ispMACH
™
4A CPLD Family
High Performance E
2
CMOS
®
In-System Programmable Logic
FEATURES
x
High-performance, E
2
CMOS 3.3-V & 5-V CPLD families
x
Flexible architecture for rapid logic designs
— Excellent First-Time-Fit
TM
and refit feature
— SpeedLocking
TM
performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
x
High speed
— 5.0ns t
PD
Commercial and 7.5ns t
PD
Industrial
— 182MHz f
CNT
x
32 to 512 macrocells; 32 to 768 registers
x
44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
x
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
x
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
TM
inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
x
Advanced E
2
CMOS process provides high-performance, cost-effective solutions
x
Supported by ispDesignEXPERT
TM
software for rapid logic development
— Supports HDL design methodologies with results optimized for ispMACH 4A
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
x
Lattice and third-party hardware programming support
— LatticePRO
TM
software for in-system programmability support on PCs and automated test
equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
2
ispMACH 4A Family
Notes:
1. Advance information. Please contact a Lattice sales representative for details on availability.
2. Preliminary information.
3. M4A3-256/128 available now in 5.5ns. Contact factory for availability of 7.5ns M4A3-256/160 and M4A3-256/192
Table 1. ispMACH 4A Device Features
3.3 V Devices
Feature
M4A3-32
2
M4A3-64
2
M4A3-96
2
M4A3-128
2
M4A3-192
2
M4A3-256
M4A3-384
2
M4A3-512
1
Macrocells
32
64
96
128
192
256
384
512
User I/O options
32
32/64
1
48
64
96
128
2
/160
1
/192
1
160/192
160/192/256
t
PD
(ns)
5.0
5.5
5.5
5.5
6.0
5.5
3
6.5
7.5
f
CNT
(MHz)
182
167
167
167
160
167
154
125
t
COS
(ns)
4.0
4.0
4.0
4.0
4.5
4.0
4.5
5.5
t
SS
(ns)
3.0
3.5
3.5
3.5
3.5
3.5
3.5
5.0
Static Power (mA)
20
25/52
1
40
55
85
110
2
/150
1
149/155
179
JTAG Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PCI Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
5 V Devices
Feature
M4A5-32
2
M4A5-64
2
M4A5-96
2
M4A5-128
2
M4A5-192
1
M4A5-256
2
Macrocells
32
64
96
128
192
256
User I/O options
32
32
48
64
96
128
t
PD
(ns)
5.0
5.5
5.5
5.5
6.0
6.5
f
CNT
(MHz)
182
167
167
167
160
154
t
COS
(ns)
4.0
4.0
4.0
4.0
4.5
5.0
t
SS
(ns)
3.0
3.5
3.5
3.5
3.5
3.5
Static Power (mA)
20
25
40
55
74
110
JTAG Compliant
Yes
Yes
Yes
Yes
Yes
Yes
PCI Compliant
Yes
Yes
Yes
Yes
Yes
Yes
ispMACH 4A Family
3
GENERAL DESCRIPTION
The ispMACH
™
4A family from Lattice offers an exceptionally flexible architecture and delivers
a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products
and software tools. The overall benefits for users are a guaranteed and predictable CPLD
solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer
densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention.
The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation.
ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std.
1149.1) interface. JTAG boundary scan testing also allows product testability on automated test
equipment for device connectivity.
All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out
retention after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A
products can deliver guaranteed fixed timing as fast as 5.0 ns t
PD
and 182 MHz f
CNT
through the
SpeedLocking feature when using up to 20 product terms per output (Table 2).
Notes:
1. C = Commercial, I = Industrial
2. Advance information. Please contact a Lattice sales representative for details on availability.
3. Preliminary information.
Table 2. ispMACH 4A Speed Grades
Device
Speed Grade
-5
-55
-6
-65
-7
-10
-12
-14
M4A3-32
3
M4A5-32
3
C
C, I
C, I
I
M4A3-64/32
3
M4A5-64/32
3
C
C, I
C, I
I
M4A3-64/64
2
C
C, I
C, I
I
M4A3-96
3
M4A5-96
3
C
C, I
C, I
I
M4A3-128
3
M4A5-128
3
C
C, I
C, I
I
M4A3-192
3
M4A5-192
2
C
C, I
C, I
I
M4A3-256/128
3
C
C
C, I
C, I
I
M4A5-256/128
3
C
C
C, I
I
M4A3-256/192
2
M4A3-256/160
2
C
C, I
I
M4A3-384
2
C
C, I
C, I
I
M4A3-512
2
C
C, I
C, I
I
4
ispMACH 4A Family
The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP),
Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), fine-
pitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table
3). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept
5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include Bus-
Friendly inputs and I/Os, a programmable power-down mode for extra power savings and
individual output slew rate control for the highest speed transition or for the lowest noise
transition.
Note:
1. Advance information. Please contact a Lattice sales representative for details on availability.
2. Preliminary information.
Table 3. ispMACH 4A Package and I/O Options
(Number of I/Os and dedicated inputs in Table)
3.3 V Devices
Package
M4A3-32
2
M4A3-64
M4A3-96
2
M4A3-128
M4A3-192
M4A3-256
M4A3-384
1
M4A3-512
1
44-pin PLCC
32+2
32+2
2
44-pin TQFP
32+2
32+2
2
48-pin TQFP
32+2
32+2
2
100-pin TQFP
64+6
1
48+8
64+6
2
100-pin PQFP
64+6
2
100-ball caBGA
64+6
1
144-pin TQFP
96+16
2
144-ball fpBGA
96+16
1
208-pin PQFP
128+14
2
, 160
1
160
160
256-ball fpBGA
128+14
2
, 192
1
192
192
256-ball BGA
128+14
2
192
388-ball fpBGA
256
5 V Devices
Package
M4A5-32
2
M4A5-64
2
M4A5-96
2
M4A5-128
2
M4A5-192
1
M4A5-256
2
44-pin PLCC
32+2
32+2
44-pin TQFP
32+2
32+2
48-pin TQFP
32+2
32+2
100-pin TQFP
48+8
64+6
100-pin PQFP
64+6
144-pin TQFP
96+16
208-pin PQFP
128+14
256-ball BGA
128+14
ispMACH 4A Family
5
FUNCTIONAL DESCRIPTION
PAL
®
blocks interconnected by a central switch matrix. The central switch matrix allows
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes.
In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms
through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the
output switch matrix. In addition, more input routing options are provided by the input switch
matrix. These resources provide the flexibility needed to fit designs efficiently.
Notes:
1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4A(3,5)-32/32.
3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do
not connect to the central switch matrix.
I/O
Pins
Clock/Input
Pins
Central Switch Matrix
I/O
Pins
I/O
Pins
Dedicated
Input Pins
PAL Block
PAL Block
Logic
Allocator
with XOR
Output/
Buried
Macrocells
33/
34/
36
16
16
Clock
Generator
Logic
Array
Output Switch Matrix
Input
Switch
Matrix
I/O Cells
16
16
8
Note 1
Note 2
Note 3
4
PAL Block
17466G-001
Figure 1. ispMACH 4A Block Diagram and PAL Block Structure
6
ispMACH 4A Family
Table 4. Architectural Summary of ispMACH 4A devices
The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O
cells internally in a PAL block (Table 4).
The central switch matrix takes all dedicated inputs and signals from the input switch matrices
and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block
still must go through the central switch matrix. This mechanism ensures that PAL blocks in
ispMACH 4A devices communicate with each other with consistent, predictable delays.
The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL
devices on a single chip. It allows the designer to think of the device not as a collection of
blocks, but as a single programmable device; the software partitions the design into PAL blocks
through the central switch matrix so that the designer does not have to be concerned with the
internal architecture of the device.
Each PAL block consists of:
x
Product-term array
x
Logic allocator
x
Macrocells
x
Output switch matrix
x
I/O cells
x
Input switch matrix
x
Clock generator
Notes:
1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix.
ispMACH 4A Devices
M4A3-64/32, M4A5-64/32
M4A3-96/48, M4A5-96/48
M4A3-128/64, M4A5-128/64
M4A3-192/96, M4A5-192/96
M4A3-256/128, M4A5-256/128
M4A3-384
M4A3-512
M4A3-32/32
M4A5-32/32
M4A3-64/64
M4A3-256/160
M4A3-256/192
Macrocell-I/O Cell
Ratio
2:1
1:1
Input Switch Matrix
Yes
Yes
1
Input Registers
Yes
No
Central Switch Matrix
Yes
Yes
Output Switch Matrix
Yes
Yes
ispMACH 4A Family
7
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic
being implemented. The inputs to the AND gates come from the central switch matrix (Table 5),
and are provided in both true and complement forms for efficient logic implementation.
Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in “product term clusters.”
The availability and distribution of product term clusters are automatically considered by the
software as it fits functions within a PAL block. The size of a product term cluster has been
optimized to provide high utilization of product terms, making complex functions using many
product terms possible. Yet when few product terms are used, there will be a minimal number
of unused—or wasted—product terms left over. The product term clusters available to each
Each product term cluster is associated with a macrocell. The size of a cluster depends on the
configuration of the associated macrocell. When the macrocell is used in synchronous mode
cluster is routed to a different macrocell, the allocator configuration is not determined by the
mode of the macrocell actually being driven. The configuration is always set by the mode of the
macrocell that the cluster will drive if not routed away, regardless of the actual routing.
In addition, there is an extra product term that can either join the basic cluster to give an
extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included
with the basic cluster, this provides for up to 20 product terms on a synchronous function that
uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18
product terms.
When the extra product term is used to extend the cluster, the value of the second XOR input
can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic
Table 5. PAL Block Inputs
Device
Number of Inputs to PAL Block
M4A3-32/32 and M4A5-32/32
M4A3-64/32 and M4A5-64/32
M4A3-64/64
M4A3-96/48 and M4A5-96/48
M4A3-128/64 and M4A5-128/64
33
33
33
33
33
M4A3-192/96 and M4A5-192/96
M4A3-256/128 and M4A5-256/128
34
34
M4A3-256/160 and M4A3-256/192
M4A3-384
M4A3-512
36
36
36
8
ispMACH 4A Family
Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32)
Output Macrocell
Available Clusters
Output Macrocell
Available Clusters
M
0
C
0
, C
1
, C
2
M
8
C
7
,
C
8
, C
9
, C
10
M
1
C
0
, C
1
, C
2
, C
3
M
9
C
8
, C
9
, C
10
, C
11
M
2
C
1
, C
2
, C
3
, C
4
M
10
C
9
, C
10
, C
11
, C
12
M
3
C
2
, C
3
, C
4
, C
5
M
11
C
10
, C
11
, C
12
, C
13
M
4
C
3
, C
4
, C
5
, C
6
M
12
C
11
, C
12
, C
13
, C
14
M
5
C
4
, C
5
, C
6
, C
7
M
13
C
12
, C
13
, C
14
, C
15
M
6
C
5
, C
6
, C
7
,
C
8
M
14
C
13
, C
14
, C
15
M
7
C