ispLSI 5512VA Data Sheet

ispLSI

5512VA

In-System Programmable

3.3V SuperWIDE™ High Density PLD

5512va_04

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

September 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Features

• SuperWIDE HIGH-DENSITY IN-SYSTEM

PROGRAMMABLE LOGIC

— 3.3V Power Supply

— User Selectable 3.3V/2.5V I/O

— 24000 PLD Gates / 512 Macrocells

— Up to 288 I/O Pins

— 512 Registers

— High-Speed Global Interconnect

— SuperWIDE 32 Generic Logic Block (GLB) Size for

Optimum Performance

— SuperWIDE Input Gating (68 Inputs) for Fast

Counters, State Machines, Address Decoders, etc.

— PCB Efficient Ball Grid Array (BGA) Package

Options

— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max = 110 MHz Maximum Operating Frequency

—

pd = 8.5 ns Propagation Delay

— Enhanced

su2 = 7 ns,

su3 (CLK0/1) = 4.5ns,

su3 (CLK2/3) = 3.5ns

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path

Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture with Single-

Level Global Routing Pool and SuperWIDE GLBs

— Wrap Around Product Term Sharing Array Supports

up to 35 Product Terms Per Macrocell

— Macrocells Support Concurrent Combinatorial and

Registered Functions

— Macrocell Registers Feature Multiple Control

Options Including Set, Reset and Clock Enable

— Four Dedicated Clock Input Pins Plus Macrocell

Product Term Clocks

— Slew and Skew Programmable I/O (SASPI/O™)

Supports Programmable Bus Hold, Pull-up, Open

Drain and Slew and Skew Rate Options

— Six Global Output Enable Terms, Two Global OE

Pins and One Product Term OE per Macrocell

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

Functional Block Diagram

Global Routing Pool

(GRP)

Boundary

Scan

Interface

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

ispLSI 5000V Description

The ispLSI 5000V Family of In-System Programmable

High Density Logic Devices is based on Generic Logic

Blocks (GLBs) of 32 registered macrocells and a single

Global Routing Pool (GRP) structure interconnecting the

GLBs.

Outputs from the GLBs drive the Global Routing Pool

(GRP) between the GLBs. Switching resources are pro-

vided to allow signals in the Global Routing Pool to drive

any or all the GLBs in the device. This mechanism allows

fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated,

programmable AND-array with 160 logic product terms

and five extra control product terms. The GLB has 68

inputs from the Global Routing Pool which are available

in both true and complement form for every product term.

Specifications

ispLSI 5512VA

Functional Block Diagram

Figure 1. ispLSI 5512VA Functional Block Diagram (388 BGA Option)

Global Routing Pool

(GRP)

Boundary

Scan

Interface

GOE0

GOE1

GSET/GRST

1. CLK2, CLK3 and TOE signals are multiplexed with I/O signals. Which I/O is multiplexed is

determined by the package type used – see table below.

TDI

TCK

TMS

TDO

CLK 1

CLK 0

CLK 3

CLK 2

VCCIO

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Generic

Logic Block

Package Type

Multiplexed Signals

388 BGA

I/O 179 / CLK2

I/O 197 / CLK3

I/O 0 / TOE

272 BGA

I/O 119 / CLK2

I/O 131 / CLK 3

I/O 0 / TOE

208 PQFP

I/O 89 / CLK2

I/O 98 / CLK 3

I/O 0 / TOE

I/O 161

I/O 160

I/O 159

I/O 158

I/O 147

I/O 146

I/O 145

I/O 144

I/O 72

I/O 73

I/O 74

I/O 75

I/O 86

I/O 87

I/O 88

I/O 89

I/O 90

I/O 91

I/O 92

I/O 93

I/O 104

I/O 105

I/O 106

I/O 107

I/O 233

I/O 232

I/O 231

I/O 230

I/O 219

I/O 218

I/O 217

I/O 216

I/O 251

I/O 250

I/O 249

I/O 248

I/O 237

I/O 236

I/O 235

I/O 234

I/O 269

I/O 268

I/O 267

I/O 266

I/O 255

I/O 254

I/O 253

I/O 252

1I/O 0 / TOE

I/O 1

I/O 2

I/O 3

I/O 14

I/O 15

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 32

I/O 33

I/O 34

I/O 35

I/O 36

I/O 37

I/O 38

I/O 39

I/O 50

I/O 51

I/O 52

I/O 53

Input Bus

Generic

Logic Block

I/O 54

I/O 55

I/O 56

I/O 57

I/O 68

I/O 69

I/O 70

I/O 71

Input Bus

Generic

Logic Block

I/O 122

I/O 123

I/O 124

I/O 125

I/O 108

I/O 109

I/O 110

I/O 111

I/O 140

I/O 141

I/O 142

I/O 143

I/O 126

I/O 127

I/O 128

I/O 129

Input Bus

Generic

Logic Block

I/O 179/CLK2

I/O 178

I/O 177

I/O 176

I/O 165

I/O 164

I/O 163

I/O 162

I/O 197/CLK3

I/O 196

I/O 195

I/O 194

I/O 183

I/O 182

I/O 181

I/O 180

I/O 215

I/O 214

I/O 213

I/O 212

I/O 201

I/O 200

I/O 199

I/O 198

Input Bus

Generic

Logic Block

I/O 287

I/O 286

I/O 285

I/O 284

I/O 273

I/O 272

I/O 271

I/O 270

Specifications

ispLSI 5512VA

ispLSI 5000V Description (Continued)

The 160 product terms are grouped in 32 sets of five and

sent into a Product Term Sharing Array (PTSA) which

allows sharing up to a maximum of 35 product terms for

a single function. Alternatively, the PTSA can be by-

passed for functions of five product terms or less. The

five extra product terms are used for shared GLB con-

trols, set, reset, clock, clock enable and output enable.

The 32 registered macrocells in the GLB are driven by the

32 outputs from the PTSA or the PTSA bypass. Each

macrocell contains a programmable XOR gate, a pro-

grammable register/latch/toggle flip-flop and the

necessary clocks and control logic to allow combinatorial

or registered operation. The macrocells each have two

outputs, which can be fed back through the Global

Routing Pool. This dual output capability from the

macrocell allows efficient use of the hardware resources.

One output can be a registered function for example,

while the other output can be an unrelated combinatorial

function. A direct register input from the I/O pad facilitates

efficient use of this feature to construct high-speed input

registers.

Macrocell registers can be clocked from one of several

global or product term clocks available on the device. A

global and product term clock enable is also provided,

eliminating the need to gate the clock to the macrocell

registers. Reset and preset for the macrocell register is

provided from both global and product term signals. The

macrocell register can be programmed to operate as a D-

type register, a D-type latch or a T-type flip flop.

The 32 outputs from the GLB can drive both the Global

Routing Pool and the device I/O cells. The Global Routing

Pool contains one line from each macrocell output and

one line from each I/O pin.

The input buffer threshold has programmable TTL/3.3V/

2.5V compatible levels. The output driver can source

4mA and sink 8mA in 3.3V mode. The output drivers have

a separate VCCIO reference input which is independent

of the main VCC supply for the device. This feature allows

the output drivers to drive either 3.3V or 2.5V output

levels while the device logic and the output current drive

is always powered from 3.3V. The output drivers also

provide individually programmable edge rates and open

drain capability. A programmable pullup resistor is pro-

vided to tie off unused inputs and a programmable

bus-hold latch is available to hold tristate outputs in their

last valid state until the bus is driven again by some

device.

The ispLSI 5000V Family features 3.3V, non-volatile in-

system programmability for both the logic and the

interconnect structures, providing the means to develop

truly reconfigurable systems. Programming is achieved

through the industry standard IEEE 1149.1-compliant

Boundary Scan interface. Boundary Scan test is also

supported through the same interface.

An enhanced, multiple cell security scheme is provided

that prevents reading of the JEDEC programming file

when secured. After the device has been secured using

this mechanism, the only way to clear the security is to

execute a bulk-erase instruction.

ispLSI 5000V Family Members

The ispLSI 5000V Family ranges from 256 macrocells to

512 macrocells and operates from a 3.3V power supply.

All family members will be available with multiple pack-

age options. The ispLSI 5000V Family device matrix

showing the various bondout options is shown in the table

below.

The interconnect structure (GRP) is very similar to Lattice's

existing ispLSI 1000, 2000 and 3000 families, but with an

enhanced interconnect structure for optimal pin locking

and logic routing. This eliminates the need for registered

I/O cells or an Output Routing Pool.

Table 1. ispLSI 5000VA Family

—

Specifications

ispLSI 5512VA

Figure 2. ispLSI 5512VA Block Diagram (288 I/O Version)

I/O

160

I/O

160

I/O

160

I/O

160

I/O

160

I/O

160

I/O

160

I/O

160

5512_384

I/O

160

I/O

160

800

SET/RESET

GOE1

GOE0

TOE

CLK1

CLK0

Global

Routing

Pool

(GRP)

Generic

Logic

Block

(GLB)

Buffers/Pins

CLK3

CLK2

Specifications

ispLSI 5512VA

Figure 3. ispLSI 5000V Generic Logic Block (GLB)

GLB_5K

0 1 2

66 67

Macrocell 0

PT 160

PT 161

PT 162

PT 163

Macrocell 1

Macrocell 15

Macrocell 31

PT 9

PT 8

PT 7

PT 6

PT 5

PT 0

PT 1

PT 2

PT 3

PT 4

PT 79

PT 78

PT 77

PT 76

PT 75

PT 159

PT 158

PT 157

PT 156

PT 155

To I/O Pad

To GRP

PTSA bypass

PT Clock

PT Reset

PT Preset

From PTSA

PTOE

Shared PT Clock 0

Shared PT (P)reset 0

Shared PT Clock 1

Shared PT (P)reset 1

Global PTOE 0 ... 5

To I/O Pad

To GRP

PTSA bypass

PT Clock

PT Reset

PT Preset

From PTSA

PTOE

Shared PT Clock 0

Shared PT (P)reset 0

Shared PT Clock 1

Shared PT (P)reset 1

Global PTOE 0 ... 5

To I/O Pad

To GRP

PTSA bypass

PT Clock

PT Reset

PT Preset

From PTSA

PTOE

Shared PT Clock 0

Shared PT (P)reset 0

Shared PT Clock 1

Shared PT (P)reset 1

Global PTOE 0 ... 5

To I/O Pad

To GRP

PTSA bypass

PT Clock

PT Reset

PT Preset

From PTSA

PTOE

Shared PT Clock 0

Shared PT (P)reset 0

Shared PT Clock 1

Shared PT (P)reset 1

Global PTOE 0 ... 5

From Global Routing Pool

PTSA

Programmable

AND Array

Global PTOE Bus

PT 164

Specifications

ispLSI 5512VA

Figure 8. Boundary Scan Waveforms and Timing Specifications

TMS

TDI

TCK

TDO

Data to be

captured

Data to be

driven out

Valid Data

Data Captured

btsu

bth

btcl

btch

btcp

btvo

btco

btoz

btcpsu

btcph

btuov

btuco

btuoz

SYMBOL

PARAMETER

MIN

MAX

UNITS

btcp

TCK [BSCAN test] clock pulse width

125

–

btch

TCK [BSCAN test] pulse width high

62.5

–

tbtcl

TCK [BSCAN test] pulse width low

62.5

–

tbtsu

TCK [BSCAN test] setup time

–

tbth

TCK [BSCAN test] hold time

–

trf

TCK [BSCAN test] rise and fall time

–

mV/ns

tbtco

TAP controller falling edge of clock to valid output

–

tbtoz

TAP controller falling edge of clock to data output disable

–

tbtvo

TAP controller falling edge of clock to data output enable

–

tbtcpsu

BSCAN test Capture register setup time

–

tbtcph

BSCAN test Capture register hold time

–

tbtuco

BSCAN test Update reg, falling edge of clock to valid output

–

tbtuoz

BSCAN test Update reg, falling edge of clock to output disable

–

tbtuov

BSCAN test Update reg, falling edge of clock to output enable

–