ispLSI 2064VE Data Sheet

ispLSI

2064VE

3.3V In-System Programmable

High Density SuperFAST™ PLD

2064ve_06

Features

• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC

— 2000 PLD Gates

— 64 and 32 I/O Pin Versions, Four Dedicated Inputs

— 64 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— 100% Functional, JEDEC and Pinout Compatible with

ispLSI 2064V Devices

• 3.3V LOW VOLTAGE 2064 ARCHITECTURE

— Interfaces with Standard 5V TTL Devices

• HIGH-PERFORMANCE E

CMOS

TECHNOLOGY

—

max = 280MHz* Maximum Operating Frequency

—

pd = 3.5ns* Propagation Delay

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

• IN-SYSTEM PROGRAMMABLE

— 3.3V In-System Programmability (ISP™) Using

Boundary Scan Test Access Port (TAP)

— Open-Drain Output Option for Flexible Bus Interface

Capability, Allowing Easy Implementation of Wired-OR

or Bus Arbitration Logic

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE

• THE EASE OF USE AND FAST SYSTEM SPEED OF

PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms

*Advanced Information

Functional Block Diagram

Global Routing Pool

(GRP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

GLB

Logic

Array

D Q

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

0139A/2064V

Description

The ispLSI 2064VE is a High Density Programmable

Logic Device available in 64 and 32 I/O-pin versions. The

device contains 64 Registers, four Dedicated Input pins,

three Dedicated Clock Input pins, two dedicated Global

OE input pins and a Global Routing Pool (GRP). The

GRP provides complete interconnectivity between all of

these elements. The ispLSI 2064VE features in-system

programmability through the Boundary Scan Test Ac-

cess Port (TAP) and is 100% IEEE 1149.1 Boundary

Scan Testable. The ispLSI 2064VE offers non-volatile

reprogrammability of the logic, as well as the intercon-

nect, to provide truly reconfigurable systems.

The basic unit of logic on the ispLSI 2064VE device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…B7 (see Figure 1). There are a total of 16 GLBs in the

ispLSI 2064VE device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

September 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

Specifications

ispLSI 2064VE

Functional Block Diagram

Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions)

The 64-I/O 2064VE contains 64 I/O cells, while the 32-

I/O version contains 32 I/O cells. Each I/O cell is directly

connected to an I/O pin and can be individually pro-

grammed to be a combinatorial input, output or

bi-directional I/O pin with 3-state control. The signal

levels are TTL compatible voltages and the output drivers

can source 4 mA or sink 8 mA. Each output can be

programmed independently for fast or slow output slew

rate to minimize overall output switching noise. Device

pins can be safely driven to 5-Volt signal levels to support

mixed-voltage systems.

Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and

two or one ORPs are connected together to make a

Megablock (see Figure 1). The outputs of the eight GLBs

are connected to a set of 32 or 16 universal I/O cells by

two or one ORPs. Each ispLSI 2064VE device contains

two Megablocks.

The GRP has as its inputs, the outputs from all of the

GLBs and all of the inputs from the bi-directional I/O cells.

All of these signals are made available to the inputs of the

GLBs. Delays through the GRP have been equalized to

minimize timing skew.

Clocks in the ispLSI 2064VE device are selected using

the dedicated clock pins. Three dedicated clock pins (Y0,

TDO/IN 2

Global Routing Pool

(GRP)

Input Bus

Output Routing Pool (ORP)

Input Bus

Output Routing Pool (ORP)

CLK 0

CLK 1

CLK 2

GOE 0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 47

I/O 46

I/O 45

I/O 44

I/O 43

I/O 42

I/O 41

I/O 40

I/O 39

I/O 38

I/O 37

I/O 36

I/O 35

I/O 34

I/O 33

I/O 32

TDI/IN 0

TMS/IN 1

I/O 4

I/O 5

BSCAN

RESET

0139B/2064VE

I/O 63

I/O 62

I/O 61

I/O 60

I/O 59

I/O 58

I/O 57

I/O 56

I/O 55

I/O 54

I/O 53

I/O 52

I/O 51

I/O 50

I/O 49

I/O 48

Input Bus

Output Routing Pool (ORP)

I/O 16

I/O 17

I/O 18

I/O 19

I/O 20

I/O 21

I/O 22

I/O 23

I/O 24

I/O 25

I/O 26

I/O 27

I/O 28

I/O 29

I/O 30

I/O 31

Output Routing Pool (ORP)

Megablock

Input Bus

GOE 1

TCK/IN 3

Generic Logic

Blocks (GLBs)

Y1, Y2) or an asynchronous clock can be selected on a

GLB basis. The asynchronous or Product Term clock

can be generated in any GLB for its own clock.

Programmable Open-Drain Outputs

In addition to the standard output configuration, the

outputs of the ispLSI 2064VE are individually program-

mable, either as a standard totem-pole output or an

open-drain output. The totem-pole output drives the

specified Voh and Vol levels, whereas the open-drain

output drives only the specified Vol. The Voh level on the

open-drain output depends on the external loading and

pull-up. This output configuration is controlled by a pro-

grammable fuse. The default configuration when the

device is in bulk erased state is totem-pole configuration.

The open-drain/totem-pole option is selectable through

the ispDesignEXPERT software tools.

TMS/IN 2

Global Routing Pool

(GRP)

Input Bus

Output Routing Pool (ORP)

CLK 0

CLK 1

CLK 2

I/O 0

I/O 1

I/O 2

I/O 3

I/O 6

I/O 7

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 23

I/O 22

I/O 21

I/O 20

I/O 19

I/O 18

I/O 17

I/O 16

TDI/IN 0

TDO/IN 1

I/O 4

I/O 5

BSCAN

0139B/2064VE.32IO

I/O 31

I/O 30

I/O 29

I/O 28

I/O 27

I/O 26

I/O 25

I/O 24

Input Bus

Output Routing Pool (ORP)

GOE1/Y0

RESET

/Y1

TCK/Y2

Output Routing Pool (ORP)

Megablock

Input Bus

GOE0/IN 3

Generic Logic

Blocks (GLBs)

Input Bus

Specifications

ispLSI 2064VE

SYMBOL

Table 2-0006/2064VE

PARAMETER

I/O Capacitance

UNITS

TYPICAL

TEST CONDITIONS

Dedicated Input Capacitance

V = 3.3V, V = 0.0V

I/O

Clock and Global Output Enable Capacitance

V = 3.3V, V = 0.0V

Absolute Maximum Ratings

Supply Voltage V

cc ...................................................

-0.5 to +5.4V

Input Voltage Applied ..................................... -0.5 to +5.6V

Off-State Output Voltage Applied .................. -0.5 to +5.6V

Storage Temperature ..................................... -65 to 150

Case Temp. with Power Applied .................... -55 to 125

Max. Junction Temp. (T

) with Power Applied ............ 150

1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional

operation of the device at these or at any other conditions above those indicated in the operational sections of this specification

is not implied (while programming, follow the programming specifications).

DC Recommended Operating Condition

Capacitance (TA=25

C, f=1.0 MHz)

Table 2-0008/2064VE

PARAMETER

MINIMUM

MAXIMUM

UNITS

Erase/Reprogram Cycles

10000

–

Cycles

Erase Reprogram Specifications

= 0

C to + 70

= -40

C to + 85

SYMBOL

Table 2-0005/2064V

PARAMETER

Supply Voltage

Input High Voltage

Input Low Voltage

MIN.

MAX.

UNITS

3.0

2.0

V – 0.5

3.6

5.25

0.8

Commercial

Industrial

Specifications

ispLSI 2064VE

Switching Test Conditions

+ 3.3V

Device

Output

Test

Point

CL includes Test Fixture and Probe Capacitance.

0213A/2064V

Figure 2. Test Load

DC Electrical Characteristics

Over Recommended Operating Conditions

SYMBOL

1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test

problems by tester ground degradation. Characterized but not 100% tested.

2. Measured using four 16-bit counters.

3. Typical values are at V = 3.3V and T = 25

4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption

section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to

estimate maximum I .

Table 2-0007/2064VE

IL-isp

PARAMETER

IL-PU

2, 4

Output Low Voltage

Output High Voltage

Input or I/O High Leakage Current

Input or I/O Low Leakage Current

BSCAN Input Low Leakage Current

I/O Active Pull-Up Current

Output Short Circuit Current

Operating Power Supply Current

I = 8 mA

I = -4 mA

≤

V (Max.)

≤

V = 3.3V, V = 0.5V

V = 0.0V, V = 3.0V

f = 1 MHz

IN IL

CC OUT

CLOCK

CONDITION

MIN.

TYP.

MAX.

UNITS

–

2.4

–

0.4

–

-10

-150

-100

–

OUT

(V – 0.2)V

≤

5.25V

Input Pulse Levels

Table 2-0003/2064VE

Input Rise and Fall Time

Input Timing Reference Levels

Output Timing Reference Levels

Output Load

GND to 3.0V

1.5V

See Figure 2

3-state levels are measured 0.5V from

steady-state active level.

≤

1.5 ns 10% to 90%

TEST CONDITION

316

Ω

348

Ω

35pF

∞

348

Ω

35pF

316

Ω

348

Ω

35pF

Active High

Active Low

316

Ω

348

Ω

5pF

∞

348

Ω

5pF

Active Low to Z

at V +0.5V

Active High to Z

at V -0.5V

Table 2-0004/2064V

Output Load Conditions (see Figure 2)

Specifications

ispLSI 2064VE

External Timing Parameters

Over Recommended Operating Conditions

pd1

UNITS

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

Table 2-0030A/2064VE

tsu2 + tco1

( )

DESCRIPTION

PARAMETER

Data Propagation Delay, 4PT Bypass, ORP Bypass

pd2

Data Propagation Delay

max

Clock Frequency with Internal Feedback

MHz

max (Ext.)

—

Clock Frequency with External Feedback

MHz

max (Tog.)

—

Clock Frequency, Max. Toggle

MHz

su1

—

GLB Reg. Setup Time before Clock, 4 PT Bypass

co1

GLB Reg. Clock to Output Delay, ORP Bypass

—

GLB Reg. Hold Time after Clock, 4 PT Bypass

su2

—

GLB Reg. Setup Time before Clock

co2

GLB Reg. Clock to Output Delay

—

GLB Reg. Hold Time after Clock

Ext. Reset Pin to Output Delay

rw1

—

Ext. Reset Pulse Duration

ptoeen

Input to Output Enable

ptoedis

Input to Output Disable

goeen

Global OE Output Enable

goedis

Global OE Output Disable

—

External Synchronous Clock Pulse Duration, High

—

External Synchronous Clock Pulse Duration, Low

-200

MIN. MAX.

—

4.5

—

200

—

0.0

4.0

—

0.0

—

4.0

—

2.5

—

2.5

—

133

200

3.0

3.5

—

4.5

—

6.0

—

8.0

5.0

7.0

-280

MIN. MAX.

—

3.5

—

280

—

Specifications

ispLSI 2064VE

External Timing Parameters

Over Recommended Operating Conditions

pd1

UNITS

-100

MIN.

TEST

COND.

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

Table 2-0030B/2064VE

tsu2 + tco1

( )

MAX.

DESCRIPTION

PARAMETER

Data Propagation Delay, 4PT Bypass, ORP Bypass

—

10.0

pd2

Data Propagation Delay

—

max

Clock Frequency with Internal Feedback

100

—

MHz

max (Ext.)

—

Clock Frequency with External Feedback

—

MHz

max (Tog.)

—

Clock Frequency, Max. Toggle

—

MHz

su1

—

GLB Reg. Setup Time before Clock, 4 PT Bypass

—

co1

GLB Reg. Clock to Output Delay, ORP Bypass

—

GLB Reg. Hold Time after Clock, 4 PT Bypass

0.0

su2

—

GLB Reg. Setup Time before Clock

8.0

co2

GLB Reg. Clock to Output Delay

—

GLB Reg. Hold Time after Clock

0.0

Ext. Reset Pin to Output Delay

—

rw1

—

Ext. Reset Pulse Duration

6.5

ptoeen

Input to Output Enable

—

ptoedis

Input to Output Disable

—

goeen

Global OE Output Enable

—

goedis

Global OE Output Disable

—

External Synchronous Clock Pulse Duration, High

5.0

—

External Synchronous Clock Pulse Duration, Low

5.0

—

100

6.5

5.0

—

6.0

—

13.5

—

15.0

9.0

13.0

-135

MIN. MAX.

—

7.5

—

135

—

0.0

6.0

—

0.0

—

5.0

—

3.5

—

3.5

—

100

143

5.0

4.0

—

5.0

—

10.0

—

12.0

7.0

10.0

Specifications

ispLSI 2064VE

Internal Timing Parameters

Over Recommended Operating Conditions

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

Table 2-0036/2064VE

Inputs

UNITS

-135

-200

MIN.

-100

MIN.

MAX.

MIN. MAX.

MAX.

DESCRIPTION

PARAMETER

20 Input Buffer Delay

din

21 Dedicated Input Delay

grp

22 GRP Delay

GLB

1ptxor

25 1 Product Term/XOR Path Delay

20ptxor

26 20 Product Term/XOR Path Delay

xoradj

27 XOR Adjacent Path Delay

gbp

28 GLB Register Bypass Delay

gsu

29 GLB Register Setup Time before Clock

30 GLB Register Hold Time after Clock

gco