Philips
Semiconductors
SCN2681
Dual asynchronous receiver/transmitter
(DUART)
Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook
1998 Sep 04
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
2
1998 Sep 04
853–1077 19970
DESCRIPTION
The Philips Semiconductors SCN2681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. It interfaces directly with microprocessors and may be
used in a polled or interrupt driven system.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable
a remote DUART transmitter when the buffer of the receiving device
is full.
Also provided on the SCN2681 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
The SCN2681 is available in three package versions: 40-pin and
28–pin, both 0.6” wide DIPs; a compact 24-pin 0.4” wide DIP; and a
44-pin PLCC.
FEATURES
•
Dual full-duplex asynchronous receiver/transmitter
•
Quadruple buffered receiver data registers
•
Programmable data format
– 5 to 8 data bits plus parity
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•
Programmable baud rate for each receiver and transmitter
selectable from:
– 22 fixed rates: 50 to 115.2k baud
•
16-bit programmable Counter/Timer
– Non-standard rates to 115.2Kb
– One user-defined rate derived from programmable
timer/counter
– External 1X or 16X clock
•
Parity, framing, and overrun error detection
•
False start bit detection
•
Line break detection and generation
•
Programmable channel mode
– Normal (full-duplex)
– Automatic echo
– Local loopback
– Remote loopback
•
Multi-function programmable 16-bit counter/timer
•
Multi-function 7-bit input port
– Can serve as clock or control inputs
– Change of state detection on four inputs
– 100k
Ω
typical pull-up resistor
•
Multi-function 8-bit output port
– Individual bit set/reset capability
– Outputs can be programmed to be status/interrupt signals
•
Versatile interrupt system
– Single interrupt output with eight maskable interrupting
conditions
– Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
•
Maximum data transfer: 1X – 1MB/sec, 16X – 125kB/sec
•
Automatic wake-up mode for multidrop applications
•
Start-end break interrupt/status
•
Detects break which originates in the middle of a character
•
On-chip crystal oscillator
•
Single +5V power supply
•
Commercial and industrial temperature ranges available
•
DIP and PLCC packages
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
Commercial
Industrial
DESCRIPTION
V
CC
= +5V +5%, T
A
= 0
°
C to +70
°
C
V
CC
= +5V +10%, T
A
= -40
°
C to +85
°
C
Plastic DIP
Plastic LCC
Plastic DIP
Plastic LCC
24-Pin
1
SCN2681AC1N24
Not available
SCN2681AE1N24
Not available
28-Pin
2
SCN2681AC1N28
Not available
SCN2681AE1N28
Not available
40-Pin
2
SCN2681AC1N40
Not available
SCN2681AE1N40
Not available
44-Pin
Not available
SCN2681AC1A44
Not available
SCN2681AE1A44
NOTES:
1. 400mil-wide Dual In-Line Package
2. 600mil-wide Dual In-Line Package
Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
3
PIN CONFIGURATIONS
PIN/FUNCTION PIN/FUNCTION
1
NC
23 NC
2
A0
24 INTRN
3
IP3
25 D6
4
A1
26 D4
5
IP1
27 D2
6
A2
28 D0
7
A3
29 OP6
8
IP0
30 OP4
9
WRN
31 OP2
10 RDN
32 OP0
11
RXDB
33 TXDA
12 NC
34 NC
13 TXDB
35 RXDA
14 OP1
36 X1/CLK
15 OP3
37 X2
16 OP5
38 RESET
17 OP7
39 CEN
18 D1
40 IP2
19 D3
41 IP6
20 D5
42 IP5
21 D7
43 IP4
22 GND
44 VCC
24
23
22
21
20
19
18
17
16
15
28
27
12
10
11
9
8
7
6
5
4
3
2
1
14
13
26
25
29
30
31
32
33
34
35
36
37
38
39
40
DIP
VCC
IP4
IP5
IP6
IP2
CEN
RESET
X2
X1/CLK
RXDA
TXDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
INTRN
A0
IP3
A1
IP1
A2
A3
IP0
WRN
RDN
RXDB
TXDB
OP1
OP3
OP5
OP7
D1
D3
D5
D7
GND
24
23
22
21
20
19
18
17
16
15
28
27
12
10
11
9
8
7
6
5
4
3
2
1
14
13
26
25
V
CC
IP2
CEN
RESET
X2
X1/CLK
RXDA
TXDA
OP0
D0
D2
D4
D6
INTRN
GND
D7
D5
D3
D1
OP1
TXDB
RXDB
RDN
WRN
A3
A2
A1
A0
DIP
1
2
3
4
5
6
7
8
9
10
11
12
23
22
21
20
19
18
17
16
15
14
13
A1
A2
A3
WRN
RDN
RXDB
TXDB
D1
D3
D5
D7
GND
DIP
24
A0
V
CC
CEN
RESET
X1/CLK
RXDA
TXDA
D0
D2
D4
D6
INTRN
1
39
17
28
40
29
18
7
PLCC
6
TOP VIEW
INDEX
CORNER
SD00084
Figure 1. Pin Configurations
Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
4
PIN DESCRIPTION
SYMBOL
APPLICABLE
TYPE
NAME AND FUNCTION
SYMBOL
40/44
28
24
TYPE
NAME AND FUNCTION
D0–D7
X
X
X
I/O
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status be-
tween the DUART and the CPU. D0 is the least significant bit.
CEN
X
X
X
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the
DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When
High, places the D0-D7 lines in the 3-State condition.
WRN
X
X
X
I
Write Strobe: When Low and CEN is also Low, the contents of the data bus is loaded into
the addressed register. The transfer occurs on the rising edge of the signal.
RDN
X
X
X
I
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed regis-
ter to be presented on the data bus. The read cycle begins on the falling edge of RDN.
A0–A3
X
X
X
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET
X
X
X
I
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts
OP0–OP7 in the High state, stops the counter/timer, and puts Channels A and B in the inac-
tive state, with the TxDA and TxDB outputs in the mark (High) state. Clears Test modes, sets
MR pointer to MR1.
INTRN
X
X
X
O
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more
of the eight maskable interrupting conditions are true.
X1/CLK
X
X
X
I
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate
frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see
Figure 7, Clock Timing.
X2
X
X
I
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin
not connected although it is permissible to ground it.
RxDA
X
X
X
I
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is
High, “space” is Low.
RxDB
X
X
X
I
Channel B Receive Serial Data Input: The least significant bit is received first. “Mark” is
High, “space” is Low.
TxDA
X
X
X
O
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first.
This output is held in the “mark” condition when the transmitter is disabled, idle or when oper-
ating in local loopback mode. “Mark” is High, “space” is Low.
TxDB
X
X
X
O
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first.
This output is held in the “mark” condition when the transmitter is disabled, idle or when oper-
ating in local loopback mode. “Mark” is High, “space” is Low.
OP0
X
X
O
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can
be deactivated automatically on receive or transmit.
OP1
X
X
O
Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can
be deactivated automatically on receive or transmit.
OP2
X
O
Output 2: General purpose output or Channel A transmitter 1X or 16X clock output, or Chan-
nel A receiver 1X clock output.
OP3
X
O
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel
B transmitter 1X clock output, or Channel B receiver 1X clock output.
OP4
X
O
Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYA/FFULLA
output.
OP5
X
O
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYB/FFULLB
output.
OP6
X
O
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYA output.
OP7
X
O
Output 7: General purpose output or Channel B open-drain, active-Low, TxRDYB output.
IP0
X
I
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin
has an internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP1
X
I
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin
has an internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP2
X
X
I
Input 2: General purpose input or counter/timer external clock input. Pin has an internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP3
X
I
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When
the external clock is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP4
X
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
m
A of current.
Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
5
PIN DESCRIPTION (Continued)
SYMBOL
APPLICABLE
TYPE
NAME AND FUNCTION
SYMBOL
40/44
28
24
TYPE
NAME AND FUNCTION
IP5
X
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When
the external clock is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP6
X
I
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
m
A of current.
V
CC
X
X
I
Power Supply: +5V supply input.
GND
X
X
I
Ground
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER
RATING
UNIT
T
A
Operating ambient temperature range
2
See Note 4
°
C
T
STG
Storage temperature range
-65 to +150
°
C
All voltages with respect to ground
3
-0.5 to +6.0
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150
o
C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
CC
supply range.
DC ELECTRICAL CHARACTERISTICS
1, 2, 3
T
A
= -40
°
C to +85
°
C, V
CC
= +5.0V
"
10%
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
V
IL
V
IH
V
IH
V
IH
V
OL
V
OH
V
OH
Input low voltage
Input high voltage (except X1/CLK)
5
Input high voltage (except X1/CLK)
4
Input high voltage (X1/CLK)
Output low voltage
Output high voltage (except o.d. outputs)
5
Output high voltage (except o.d. outputs)
4
I
OL
= 2.4mA
I
OH
= -400
µ
A
I
OH
= -400
µ
A
2
2.5
4
2.4
2.9
0.8
0.4
V
V
V
V
V
V
V
I
IL
I
LL
I
X1L
I
X1H
I
X2L
I
X2H
I
OC
I
OCC
Input leakage current
Data bus 3-stage leakage current
X1/CLK low input current
X1/CLK high input current
X2 low input current
X2 high input current
Open-collector output leakage current
Power supply current
V
IN
= 0 to V
CC
V
O
= 0.4 to V
CC
V
IN
= 0, X2 grounded
V
IN
= 0, X2 floated
V
IN
= V
CC
, X2 grounded
V
IN
= V
CC
, X2 floated
V
IN
= 0, X1/CLK floated
V
IN
= V
CC
, X1/CLK floated
V
O
= 0.4 to V
CC
0
°
C to +70
°
C version
-40
°
C to +85
°
C version
-10
-10
-4
-3
-1
0
-100
0
-10
-2
-1.5
0.2
3.5
-30
+30
10
10
0
0
1
10
0
100
10
150
175
µ
A
µ
A
mA
mA
mA
mA
µ
A
µ
A
µ
A
mA
mA
NOTES:
1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
CC
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages
of 0.8V and 2.0V as appropriate.
3. Typical values are at +25
°
C, typical supply voltages, and typical processing parameters.
4. T
A
< 0
°
C
5. T
A
> 0
°
C
Philips Semiconductors
Product specification
SCN2681
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
6
AC CHARACTERISTICS
T
A
= -40
°
C to +85
°
C
1
, V
CC
= +5.0V
"
10%
2, 3, 4, 5
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
Min
Typ
Max
UNIT
Reset Timing (Figure 3)
t
RES
RESET pulse width
200
ns
Bus Timing (Figure 4)
6
t
AS
A0-A3 setup time to RDN, WRN Low
10
ns
t
AH
A0-A3 hold time from RDN, WRN Low
100
ns
t
CS
CEN setup time to RDN, WRN Low
0
ns
t
CH
CEN hold time from RDN, WRN High
0
ns
t
RW
WRN, RDN pulse width
225
ns
t
DD
Data valid after RDN Low
175
ns
t
DF
Data bus floating after RDN High
100
ns
t
DS
Data setup time before WRN High
100
ns
t
DH
Data hold time after WRN High
20
ns
t
RWD
High time between READs and/or WRITE
7, 8
200
ns
Port Timing (Figure 5)
6
t
PS
Port input setup time before RDN Low
0
ns
t
PH
Port input hold time after RDN High
0
ns
t
PD
Port output valid after WRN High
400
ns
Interrupt Timing (Figure 6)
t
IR
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
300
ns
Write THR (TxRDY interrupt)
300
ns
Reset command (delta break interrupt)
300
ns
Stop C/T command (counter interrupt)
300
ns
Read IPCR (input port change interrupt)
300
ns
Write IMR (clear of interrupt mask bit)
300
ns
Clock Timing (Figure 7)
10
t
CLK
X1/CLK High or Low time
100
ns
f
CLK
X1/CLK frequency
2.0
3.6864
4.0
MHz
t
CTC
CTCLK (IP2) High or Low time
100
ns
f
CTC
CTCLK (IP2) frequency
0
4.0
MHz
t
RX
9
RxC High or Low time
220
ns
f
RX
9
RxC frequency (16X)
(1X)
0
0
2.0
1.0
MHz
MHz
t
TX
9
TxC High or Low time
220
ns
f
TX
9
TxC frequency (16X)
(1X)
0
0
2.0
1.0
MHz
MHz
Transmitter Timing (Figure 8)
t
TXD
9
TxD output delay from TxC external clock input on IP pin
350
ns
t
TCS
9
Output delay from TxC low at OP pin to TxD data output
0
150
ns
Receiver Timing (Figure 10)
t
RXS
9
RxD data setup time before RxC high at external clock input on IP pin
240
ns
t
RXH
9
RxD data hold time after RxC high at external clock input on IP pin
200
ns
NOTES:
1. For operating at elevated temperatures, the device must be derated based on +150
°
C maximum junction temperature.
2. Parameters are valid over specified temperature range.
3. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of < 20ns. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V
and 2.0V as appropriate.
4. Typical values are at +25
°
C, typical supply voltages, and typical processing parameters.
5. Test condition for outputs: C
L
= 150pF, except interrupt outputs. Test condition for interrupt outputs: C
L
= 50pF, R
L
= 2.7k
Ω
to V
CC
.
6. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN, CEN and RDN (also CEN and WRN) are ANDed
internally. As a consequence, the signal asserted last initiates the cycle and the signal n