Philips
Semiconductors
SCC2692
Dual asynchronous receiver/transmitter
(DUART)
Product specification
Supersedes data of 1998 Feb 19
IC19 Data Handbook
1998 Sep 04
INTEGRATED CIRCUITS
Philips Semiconductors
Product specification
SCC2692
Dual asynchronous receiver/transmitter (DUART)
2
1998 Sep 04
853–0895 19971
DESCRIPTION
The Philips Semiconductors SCC2692 Dual Universal
Asynchronous Receiver/Transmitter (DUART) which is compatible
with the SCN2681. It is a single-chip CMOS-LSI communications
device that provides two full-duplex asynchronous
receiver/transmitter channels in a single package. It interfaces
directly with microprocessors and may be used in a polled or
interrupt driven system.
The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.
Each receiver is quadruply buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable a
remote DUART transmitter when the receiver buffer is full.
Also provided on the SCC2692 are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.
FEATURES
•
Dual full-duplex asynchronous receiver/transmitters
•
Quadruple buffered receiver data register
•
Programmable data format
– 5 to 8 data bits plus parity
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments
•
16-bit programmable Counter/Timer
•
Programmable baud rate for each receiver and transmitter
selectable from:
– 22 fixed rates: 50 to 115.2k baud
– Non-standard rates to 115.2Kb
– Non-standard user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock
•
Parity, framing, and overrun error detection
•
False start bit detection
•
Line break detection and generation
•
Programmable channel mode
– Normal (full-duplex)
– Automatic echo
– Local loopback
– Remote loopback
– Multidrop mode (also called ‘wake-up’ or ‘9-bit’)
•
Multi-function 7-bit input port
– Can serve as clock or control inputs
– Change of state detection on four inputs
– Inputs have typically >100k pull-up resistors
•
Multi-function 8-bit output port
– Individual bit set/reset capability
– Outputs can be programmed to be status/interrupt signals
•
Versatile interrupt system
– Single interrupt output with eight maskable interrupting
conditions
– Output port can be configured to provide a total of up to six
separate wire-ORable interrupt outputs
•
Maximum data transfer rates: 1X – 1MB/sec, 16X – 125kB/sec
•
Automatic wake-up mode for multidrop applications
•
Start-end break interrupt/status
•
Detects break which originates in the middle of a character
•
On-chip crystal oscillator
•
Power down mode
•
Receiver timeout mode
•
Commercial and industrial temperature range versions
•
TTL compatible
•
Single +5V power supply
ORDERING INFORMATION
COMMERCIAL
INDUSTRIAL
DESCRIPTION
V
CC
= +5V +10%,
T
A
= 0 to +70
°
C
V
CC
= +5V +10%,
T
A
= -40 to +85
°
C
DWG #
40-Pin Plastic Dual In-Line Package (DIP)
1
SCC2692AC1N40
SCC2692AE1N40
SOT129-1
28-Pin Plastic Dual In-Line Package (DIP)
1
SCC2692AC1N28
SCC2692AE1N28
SOT117-1
44-Pin Plastic Leaded Chip Carrier (PLCC) Package
SCC2692AC1A44
SCC2692AE1A44
SOT187-2
44–Pin Plastic Quad Flat Pack (PQFP)
SCC2692AC1B44
SCC2692AE1B44
SOT307–2
NOTE:
1. For availability, please contact factory.
Philips Semiconductors
Product specification
SCC2692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
3
PIN/FUNCTION PIN/FUNCTION
1
NC
23 NC
2
A0
24 INTRN
3
IP3
25 D6
4
A1
26 D4
5
IP1
27 D2
6
A2
28 D0
7
A3
29 OP6
8
IP0
30 OP4
9
WRN
31 OP2
10 RDN
32 OP0
11
RXDB
33 TXDA
12 NC
34 NC
13 TXDB
35 RXDA
14 OP1
36 X1/CLK
15 OP3
37 X2
16 OP5
38 RESET
17 OP7
39 CEN
18 D1
40 IP2
19 D3
41 IP6
20 D5
42 IP5
21 D7
43 IP4
22 GND
44 V
CC
24
23
22
21
20
19
18
17
16
15
28
27
12
10
11
9
8
7
6
5
4
3
2
1
14
13
26
25
29
30
31
32
33
34
35
36
37
38
39
40
DIP
VCC
IP4
IP5
IP6
IP2
CEN
RESET
X2
X1/CLK
RxDA
TxDA
OP0
OP2
OP4
OP6
D0
D2
D4
D6
INTRN
A0
IP3
A1
IP1
A2
A3
IP0
WRN
RDN
RxDB
TxDB
OP1
OP3
OP5
OP7
D1
D3
D5
D7
GND
24
23
22
21
20
19
18
17
16
15
28
27
12
10
11
9
8
7
6
5
4
3
2
1
14
13
26
25
V
CC
IP2
CEN
RESET
X2
X1/CLK
RxDA
TxDA
OP0
D0
D2
D4
D6
INTRN
GND
D7
D5
D3
D1
OP1
TxDB
RxDB
RDN
WRN
A3
A2
A1
A0
DIP
1
39
17
28
40
29
18
7
PLCC
6
INDEX
CORNER
SD00131
PIN/FUNCTION PIN/FUNCTION
1
A3
23 N/C
2
IP0
24 OP6
3
WRN
25 OP4
4
RDN
26 OP2
5
RxDB
27 OP0
6
TxDB
28 TxDA
7
OP1
29 RxDA
8
OP3
30 X1/CLK
9
OP5
31 X2
10 OP7
32 RESET
11
N/C
33 CEN
12 D1
34 IP2
13 D3
35 IP6
14 D5
36 IP5
15 D7
37 IP4
16 GND
38 V
CC
17 GND
39 V
CC
18 INTRN
40 A0
19 D6
41 IP3
20 D4
42 A1
21 D2
43 IP1
22 D0
44 A2
TOP VIEW
33
11
22
34
23
12
1
PQFP
44
TOP VIEW
Figure 1. Pin Configurations
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER
RATING
UNIT
T
A
Operating ambient temperature range
2
Note 4
°
C
T
STG
Storage temperature range
-65 to +150
°
C
V
CC
Voltage from V
CC
to GND
3
-0.5 to +7.0
V
V
S
Voltage from any pin to GND
3
-0.5 to V
CC
+0.5
V
Package power dissipation
DIP28
1.22
W
P
Package power dissipation
DIP40
2.97
W
P
D
Package power dissipation
PLCC44
2.66
W
Package power dissipation
PQFP44
2.08
W
Derating factor above 25
°
C
DIP28
19
mW/
°
C
Derating factor above 25
°
C
DIP40
24
mW/
°
C
Derating factor above 25
°
C
PLCC44
21
mW/
°
C
Derating factor above 25
°
C
PQFP44
17
mW/
°
C
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
Philips Semiconductors
Product specification
SCC2692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
4
BLOCK DIAGRAM
8
D0–D7
RDN
WRN
CEN
A0–A3
RESET
INTRN
X1/CLK
X2
4
BUS BUFFER
OPERATION CONTROL
ADDRESS
DECODE
R/W CONTROL
INTERRUPT CONTROL
IMR
ISR
TIMING
BAUD RATE
GENERATOR
CLOCK
SELECTORS
COUNTER/
TIMER
XTAL OSC
CSRA
CSRB
ACR
CTLR
CHANNEL A
TRANSMIT
HOLDING REG
TRANSMIT
SHIFT REGISTER
RECEIVE
HOLDING REG (3)
RECEIVE
SHIFT REGISTER
MRA1, 2
CRA
SRA
INPUT PORT
CHANGE OF
STATE
DETECTORS (4)
OUTPUT PORT
FUNCTION
SELECT LOGIC
OPCR
TxDA
RxDA
IP0-IP6
OP0-OP7
VCC
GND
CONTROL
TIMING
INTERNAL
DA
T
ABUS
CHANNEL B
(AS ABOVE)
IPCR
ACR
OPR
CTLR
U
RxDB
TxDB
8
7
SD00132
Figure 2. Block Diagram
Philips Semiconductors
Product specification
SCC2692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
5
PIN DESCRIPTION
SYMBOL
APPLICABLE
TYPE
NAME AND FUNCTION
SYMBOL
40,44
28
TYPE
NAME AND FUNCTION
D0-D7
X
X
I/O
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the
DUART and the CPU. D0 is the least significant bit.
CEN
X
X
I
Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART
are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs. When High, places the
D0-D7 lines in the 3-State condition.
WRN
X
X
I
Write Strobe: When Low and CEN is also Low, the contents of the data bus are loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
RDN
X
X
I
Read Strobe: When Low and CEN is also Low, causes the contents of the addressed register to be
presented on the data bus. The read cycle begins on the falling edge of RDN.
A0-A3
X
X
I
Address Inputs: Select the DUART internal registers and ports for read/write operations.
RESET
X
X
I
Reset: A High level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0-OP7 in
the High state, stops the counter/timer, and puts Channels A and B in the inactive state, with the TxDA
and TxDB outputs in the mark (High) state. Resets Test modes, MR pointer set to MR1.
INTRN
X
X
O
Interrupt Request: Active-Low, open-drain, output which signals the CPU that one or more of the
eight maskable interrupting conditions are true.
X1/CLK
X
X
I
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.
X2
X
X
I
Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not
connected although it is permissible to ground it.
RxDA
X
X
I
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
“space” is Low.
RxDB
X
X
I
Channel B Receiver Serial Data Input: The least significant bit is received first. “Mark” is High,
“space” is Low.
TxDA
X
X
O
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback
mode. “Mark” is High, “space” is Low.
TxDB
X
X
O
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output
is held in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local
loopback mode. ‘Mark’ is High, ‘space’ is Low.
OP0
X
X
O
Output 0: General purpose output or Channel A request to send (RTSAN, active-Low). Can be
deactivated automatically on receive or transmit.
OP1
X
X
O
Output 1: General purpose output or Channel B request to send (RTSBN, active-Low). Can be
deactivated automatically on receive or transmit.
OP2
X
O
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A
receiver 1X clock output.
OP3
X
O
Output 3: General purpose output or open-drain, active-Low counter/timer output or Channel B
transmitter 1X clock output, or Channel B receiver 1X clock output.
OP4
X
O
Output 4: General purpose output or Channel A open-drain, active-Low, RxRDYAN/FFULLAN output.
OP5
X
O
Output 5: General purpose output or Channel B open-drain, active-Low, RxRDYBN/FFULLBN output.
OP6
X
O
Output 6: General purpose output or Channel A open-drain, active-Low, TxRDYAN output.
OP7
X
O
Output 7: General purpose output, or Channel B open-drain, active-Low, TxRDYBN output.
IP0
X
I
Input 0: General purpose input or Channel A clear to send active-Low input (CTSAN). Pin has an
internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP1
X
I
Input 1: General purpose input or Channel B clear to send active-Low input (CTSBN). Pin has an
internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP2
X
X
I
Input 2: General purpose input or counter/timer external clock input. Pin has an internal V
CC
pull-up
device supplying 1 to 4
m
A of current.
IP3
X
I
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP4
X
I
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP5
X
I
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the
external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the
clock. Pin has an internal V
CC
pull-up device supplying 1 to 4
m
A of current.
IP6
X
I
Input 6: General purpose input or Channel B receiver external clock input (RxCB). When the external
clock is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an
internal V
CC
pull-up device supplying 1 to 4
m
A of current.
V
CC
X
X
I
Power Supply: +5V supply input.
GND
X
X
I
Ground
Philips Semiconductors
Product specification
SCC2692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
6
DC ELECTRICAL CHARACTERISTICS
1, 2, 3
SYM-
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
BOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
V
IL
Input low voltage
0.8
V
V
IH
Input high voltage (except X1/CLK)
6
2.0
V
V
IH
Input high voltage (except X1/CLK)
7
2.5
V
V
IH
Input high voltage (X1/CLK)
0.8 V
CC
V
V
OL
Output low voltage
I
OL
= 2.4mA
0.4
V
V
OH
Output high voltage (except OD outputs)
4
I
OH
= -400
µ
A
V
CC
-0.5
V
I
IX1PD
X1/CLK input current - power down
V
IN
= 0 to V
CC
-10
+10
µ
A
I
ILX1
X1/CLK input low current - operating
V
IN
= 0
-75
0
µ
A
I
IHX1
X1/CLK input high current - operating
V
IN
= V
CC
0
75
µ
A
I
OHX2
X2 output high current - operating
V
OUT
= V
CC
, X1 = 0
0
+75
µ
A
I
OHX2S
X2 output high short circuit current - operating
V
OUT
= 0, X1 = 0
-10
-1
mA
I
OLX2
X2 output low current - operating
V
OUT
= 0, X1 = V
CC
-75
0
µ
A
I
OLX2S
X2 output low short circuit current - operating and power down
V
OUT
= V
CC
, X1 = V
CC
1
10
mA
Input leakage current:
I
I
All except input port pins
V
IN
= 0 to V
CC
-10
+10
µ
A
Input port pins
V
IN
= 0 to V
CC
-20
+10
µ
A
I
OZH
Output off current high, 3-state data bus
V
IN
= V
CC
10
µ
A
I
OZL
Output off current low, 3-state data bus
V
IN
= 0V
-10
µ
A
I
ODL
Open-drain output low current in off-state
V
IN
= 0
-10
µ
A
I
ODH
Open-drain output high current in off-state
V
IN
= V
CC
10
µ
A
Power supply current
5
I
CC
Operating mode
CMOS input levels
10
mA
Power down mode
8
CMOS input levels
2
10
m
A
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25
°
C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C
L
= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 50pF, R
L
= 2.7K
Ω
to V
CC
.
5. All outputs are disconnected. Inputs are switching between CMOS levels of V
CC
-0.2V and V
SS
+ 0.2V.
6. T
A
> 0
°
C
7. T
A
< 0
°
C
8. See UART application note for 5
µ
A.
AC CHARACTERISTICS
1, 2, 4
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
Min
Typ
3
Max
UNIT
Reset Timing (See Figure 3)
t
RES
RESET pulse width
200
ns
Bus Timing
5
(See Figure 4)
t
AS
A0-A3 setup time to RDN, WRN Low
10
ns
t
AH
A0-A3 hold time from RDN, WRN Low
100
ns
t
CS
CEN setup time to RDN, WRN Low
0
ns
t
CH
CEN hold time from RDN, WRN High
0
ns
t
RW
WRN, RDN pulse width
225
ns
t
DD
Data valid after RDN Low
175
ns
t
DA
RDN Low to data bus active
7
15
ns
t
DF
Data bus floating after RDN High
125
ns
t
DI
RDN High to data bus invalid
7
20
ns
t
DS
Data setup time before WRN High
100
ns
t
DH
Data hold time after WRN High
20
ns
t
RWD
High time between reads and/or writes
5, 6
200
ns
Philips Semiconductors
Product specification
SCC2692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
7