Am28F256

FINAL

Publication# 11560

Rev: G Amendment/+2

Issue Date: January 1998

Am28F256

256 Kilobit (32 K x 8-Bit)

CMOS 12.0 Volt, Bulk Erase Flash Memory

DISTINCTIVE CHARACTERISTICS

High performance

— 70 ns maximum access time

CMOS Low power consumption

— 30 mA maximum active current

— 100 µA maximum standby current

— No data retention power consumption

Compatible with JEDEC-standard byte-wide

32-Pin EPROM pinouts

— 32-pin PDIP

— 32-pin PLCC

— 32-pin TSOP

10,000 write/erase cycles minimum

Write and erase voltage 12.0 V

Latch-up protected to 100 mA

from –1 V to V

+1 V

Flasherase

Electrical Bulk Chip-Erase

— One second typical chip-erase

Flashrite Programming

— 10 µs typical byte-program

— 0.5 second typical chip program

Command register architecture for

microprocessor/microcontroller compatible

write interface

On-chip address and data latches

Advanced CMOS flash memory technology

— Low cost single transistor memory cell

Automatic write/erase pulse stop timer

GENERAL DESCRIPTION

The Am28F256 is a 256 K Flash memory organized as

32 Kbytes of 8 bits each. AMD’s Flash memories offer

the most cost-effective and reliable read/write non-

volatile random access memory. The Am28F256 is

packaged in 32-pin PDIP, PLCC, and TSOP versions. It

is designed to be reprogrammed and erased in-system

or in standard EPROM programmers. The Am28F256

is erased when shipped from the factory.

The standard Am28F256 offers access times as fast as

70 ns, allowing operation of high-speed microproces-

sors without wait states. To eliminate bus contention,

the Am28F256 has separate chip enable (CE

) and

output enable (OE

) controls.

AMD’s Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

Am28F256 uses a command register to manage this

functionality, while maintaining a standard JEDEC

Flash Standard 32-pin pinout. The command register

allows for 100% TTL level control inputs and fixed

power supply levels during erase and programming.

AMD’s Flash technology reliably stores memor y

contents even after 10,000 erase and program cycles.

The AMD cell is designed to optimize the erase and

programming mechanisms. In addition, the combina-

tion of advanced tunnel oxide processing and low

internal electric fields for erase and programming

operations produces reliable cycling. The Am28F256

uses a 12.0V

5% V

high voltage input to perform

the Flasherase

and Flashrite

algorithms.

The highest degree of latch-up protection is achieved

with AMD’s proprietar y non-epi process. Latch-up

protection is provided for stresses up to 100 milliamps

on address and data pins from –1 V to V

+1 V.

The Am28F256 is byte programmable using 10 µs

programming pulses in accordance with AMD ’s

Flashrite programming algorithm. The typical room

temperature programming time of the Am28F256 is a

half a second. The entire chip is bulk erased using

10 ms erase pulses according to AMD’s Flasherase

alrogithm. Typical erasure at room temperature is

accomplished in less than one second. The windowed

package and the 15-20 minutes required for EPROM

erasure using ultra-violet light are eliminated.

Am28F256

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as inputs to an internal state-machine which

controls the erase and programming circuitry. During

write cycles, the command register internally latches ad-

dress and data needed for the programming and erase

operations. For system design simplification, the

Am28F256 is designed to support either WE

or CE

controlled writes. During a system write cycle, ad-

dresses are latched on the falling edge of WE

or CE

whichever occurs last. Data is latched on the rising edge

of WE

or CE

whichever occurs first. To simplify the fol-

lowing discussion, the WE

pin is used as the write cycle

control pin throughout the rest of this text. All setup and

hold times are with respect to the WE

signal.

AMD’s Flash technology combines years of EPROM

and EEPROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The

Am28F256 electrically erases all bits simultaneously

using Fowler-Nordheim tunneling. The bytes are

programmed one byte at a time using the EPROM

programming mechanism of hot electron injection.

BLOCK DIAGRAM

PRODUCT SELECTOR GUIDE

Family Part Number

Am28F256

Speed Options (V

= 5.0 V

10%)

-70

-90

-120

-150

-200

Max Access Time (ns)

120

150

200

CE# (E#) Access (ns)

120

150

200

OE# (G#) Access (ns)

Erase

Voltage

Switch

Command

Program

Voltage

Switch

Chip Enable

Output Enable

Logic

Y-Decoder

X-Decoder

Y-Gating

262,144

Bit

Cell Matrix

11560F-1

A0–A14

OE#

CE#

WE#

VSS

VCC

To Array

DQ0–DQ7

Input/Output

Buffers

Data

Latch

VPP

Address

Latch

Low VCC

Detector

Program/Erase

Pulse Timer

State

Control

Am28F256

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am28F256

256 Kilobit (32 K x 8-Bit) CMOS Flash Memory

AM28F256

-70

OPTIONAL PROCESSING

Blank = Standard Processing

= Burn-In

Contact an AMD representative for more information.

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

P = 32-Pin Plastic DIP (PD 032)

J = 32-Pin Rectangular Plastic Leaded Chip

Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

Valid Combinations

AM28F256-70

PC, PI, PE,

JC, JI, JE,

EC, EI, EE,

FC, FI, FE

AM28F256-90

AM28F256-120

AM28F256-150

AM28F256-200

Am28F256

PIN DESCRIPTION

A0–A14

ddress Inputs for memory locations. Internal latches

hold addresses during write cycles.

)

Chip Enable active low input activates the chip’s control

logic and input buffers. Chip Enable high will deselect

the device and operates the chip in stand-by mode.

DQ0–DQ7

Data Inputs during memor y write cycles. Internal

latches hold data during write cycles. Data Outputs

during memory read cycles.

No Connect-corresponding pin is not connected

internally to the die.

)

Output Enable active low input gates the outputs of the

device through the data buffers dur ing memor y

read cycles. Output Enable is high during command

sequencing and program/erase operations.

Power supply for device operation. (5.0 V

5% or 10%)

Program voltage input. V

must be at high voltage in

order to write to the command register. The command

memory array contents. Memory contents cannot be

altered when V

≤

+2 V.

Ground

)

Write Enable active low input controls the write function

of the command register to the memory array. The

target address is latched on the falling edge of the

Write Enable pulse and the appropriate data is latched

on the rising edge of the pulse. Write Enable high

inhibits writing to the device.

Am28F256

BASIC PRINCIPLES

The device uses 100% TTL-level control inputs to

manage the command register. Erase and repro-

gramming operations use a fixed 12.0 V

5% high

voltage input.

Read Only Memory

Without high V

voltage, the device functions as a

read only memor y and operates like a standard

EPROM. The control inputs still manage traditional

read, standby, output disable, and Auto select modes.

Command Register

The command register is enabled only when high volt-

age is applied to the V

pin. The erase and repro-

gramming operations are only accessed via the

for erase and reprogramming operations. The tradi-

tional read, standby, output disable, and Auto select

modes are available via the register.

The device’s command register is written using stan-

dard microprocessor write timings. The register con-

trols an internal state machine that manages all device

operations. For system design simplification, the de-

vice is designed to support either WE# or CE# con-

trolled writes. During a system write cycle, addresses

are latched on the falling edge of WE# or CE# which-

ever occurs last. Data is latched on the rising edge of

WE# or CE# whichever occur first. To simplify the fol-

lowing discussion, the WE# pin is used as the write

cycle control pin throughout the rest of this text. All

setup and hold times are with respect to the WE# sig-

nal.

Overview of Erase/Program Operations

Flasherase™ Sequence

A multiple step command sequence is required to

erase the Flash device (a two-cycle Erase command

and repeated one cycle verify commands).

Note: The Flash memory array must be completely

programmed to 0’s prior to erasure. Refer to the

Flashrite™ Programming Algorithm.

1. Erase Setup: Write the Setup Erase command to

the command register.

2. Erase: Write the Erase command (same as Setup

Erase command) to the command register again.

The second command initiates the erase operation.

The system software routines must now time-out

the erase pulse width (10 ms) prior to issuing the

Erase-verify command. An integrated stop timer

prevents any possibility of overerasure.

3. Erase-Verify: Write the Erase-verify command to

the command register. This command terminates

the erase operation. After the erase operation,

each byte of the array must be verified. Address in-

formation must be supplied with the Erase-verify

command. This command verifies the margin and

outputs the addressed byte in order to compare the

a r r a y d a t a w i t h F F h d a t a ( B y t e e r a s e d ) .

After successful data verification the Erase-verify

command is written again with new address infor-

mation. Each byte of the array is sequentially veri-

fied in this manner.

If data of the addressed location is not verified, the

Erase sequence is repeated until the entire array is

successfully verified or the sequence is repeated

1000 times.

Flashrite

Programming Sequence

A three step command sequence (a two-cycle Program

command and one cycle Verify command) is required

to program a byte of the Flash array. Refer to the Flash-

rite

Algorithm.

1. Program Setup: Write the Setup Program com-

mand to the command register.

2. Program: Write the Program command to the com-

mand register with the appropriate Address and

Data. The system software routines must now time-

out the program pulse width (10 µs) prior to issuing

the Program-verify command. An integrated stop

timer prevents any possibility of overprogramming.

3. Program-Verify: Write the Program-verify com-

mand to the command register. This command ter-

minates the programming operation. In addition,

this command verifies the margin and outputs the

byte just programmed in order to compare the array

data with the original data programmed. After suc-

cessful data verification, the programming se-

quence is initiated again for the next byte address to

be programmed.

If data is not verified successfully, the Program se-

quence is repeated until a successful comparison is

verified or the sequence is repeated 25 times.

Data Protection

The device is designed to offer protection against acci-

dental erasure or programming caused by spurious

system level signals that may exist during power transi-

tions. The device powers up in its read only state. Also,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences.

The device also incorporates several features to pre-

vent inadvertent write cycles resulting from V

power-

up and power-down transitions or system noise.

Low V

Write Inhibit

To avoid initiation of a write cycle during V

power-up

and power-down, the device locks out write cycles for

Am28F256

< V

LKO

(see DC Characteristics section for

voltages). When V

< V

LKO

, the command register is

disabled, all inter nal program/erase circuits are

disabled, and the device resets to the read mode. The

device ignores all writes until V

> V

LKO

. The user

must ensure that the control pins are in the correct logic

state when V

> V

LKO

to prevent uninitentional writes.

Write Pulse “Glitch” Protection

Noise pulses of less than 10 ns (typical) on OE#, CE#

or WE# will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE# = V

, CE#

= V

or WE# = V

. To initiate a write cycle CE# and

WE# must be a logical zero while OE# is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE# = CE# = V

and

OE# = V

will not accept commands on the rising

edge of WE#. The internal state machine is automat-

ically reset to the read mode on power-up.

FUNCTIONAL DESCRIPTION

Description Of User Modes

Table 1.

Am28F256 Device Bus Operations (Notes 7 and 8)

Legend:

X = Don’t care, where Don’t Care is either V

or V

levels. V

PPL

= V

+ 2 V. See DC Characteristics for voltage levels

of V

PPH

. 0 V < An < V

+ 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).

Notes:

1. V

PPL

may be grounded, connected with a resistor to ground, or < V

+ 2.0 V. V

PPH

is the programming voltage specified for

the device. Refer to the DC characteristics. When V

= V

PPL

, memory contents can be read but not written or erased.

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.

3. 11.5 < V

< 13.0 V. Minimum V

rise time and fall time (between 0 and V

voltages) is 500 ns.

4. Read operation with V

= V

PPH

may access array data or the Auto select codes.

5. With V

at high voltage, the standby current is I

+ I

(standby).

6. Refer to Table 3 for valid D

during a write operation.

7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either V

or V

levels. In the Auto select mode all

addresses except A

and A

must be held at V

8. If V

≤

1.0 Volt, the voltage difference between V

and V

should not exceed 10.0 volts. Also, the Am28F256 has a V

rise time and fall time specification of 500 ns minimum.

Operation

CE#

(E#)

OE#

(G#)

WE#

(W#)

(Note 1)

I/O

Read-Only

Read

PPL

OUT

Standby

PPL

HIGH Z

Output Disable

PPL

HIGH Z

Auto-select Manufacturer

Code (Note 2)

PPL

(Note 3)

CODE

(01h)

Auto-select Device

Code (Note 2)

PPL

(Note 3)

CODE

(A1h)

Read/Write

Read

PPH

OUT

(Note 4)

Standby (Note 5)

PPH

HIGH Z

Output Disable

PPH

HIGH Z

Write

PPH

(Note 6)

Am28F256

READ ONLY MODE

When V

is less than V

+ 2 V, the command register

is inactive. The device can either read array or autose-

lect data, or be standby mode.

Read

The device functions as a read only memory when V

< V

+ 2 V.

The device has two control functions. Both

must be satisfied in order to output data. CE# controls

power to the device. This pin should be used for spe-

cific device selection. OE# controls the device outputs

and should be used to gate data to the output pins if a

device is selected.

Address access time t

ACC

is equal to the delay from

stable addresses to valid output data. The chip enable

access time t

is the delay from stable addresses and

stable CE# to valid data at the output pins. The output

enable access time is the delay from the falling edge of

OE# to valid data at the output pins (assuming the ad-

dresses have been stable at least t

ACC

–t

Standby Mode

The device has two standby modes. The CMOS

standby mode (CE# input held at V

0.5 V), con-

sumes less than 100 µA of current. TTL standby mode

(CE# is held at V

) reduces the current requirements

to less than 1mA. When in the standby mode the out-

puts are in a high impedance state, independent of the

OE# input.

If the device is deselected during erasure, program-

ming, or program/erase verification, the device will

draw active current until the operation is terminated.

Output Disable

Output from the device is disabled when OE# is at a

logic high level. When disabled, output pins are in a

high impedance state.

Auto Select

Flash memories can be programmed in-system or in a

standard PROM programmer. The device may be sol-

dered to the circuit board upon receipt of shipment and

programmed in-system. Alternatively, the device may

initially be programmed in a PROM programmer prior

to soldering the device to the board.

The Auto select mode allows the reading out of a binary

code from the device that will identify its manufacturer

and type. This mode is intended for the purpose

of automatically matching the device to be pro-

grammed with its corresponding programming algo-

r ith m. Th is mo de is f unc tio nal ove r t he en tir e

temperature range of the device.

Programming In A PROM Programmer

To activate this mode, the programming equipment

must force V

(11.5 V to 13.0 V) on address A9. Two

identifier bytes may then be sequenced from the device

outputs by toggling address A

from V

to V

. All other

address lines must be held at V

, and V

must

less than or equal to V

+ 2.0 V while using this Auto

select mode. Byte 0 (A0 = V

) represents the manufac-

turer code and byte 1 (A0 = V

) the device identifier

code. For the device these two bytes are given in Table

2 below. All identifiers for manufacturer and device

codes will exhibit odd parity with the MSB (DQ7) de-

fined as the parity bit.

Table 2.

Am28F256 Auto Select Code

Type

Code

(HEX)

Manufacturer Code

Device Code