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1996 Microchip Technology Inc.

Preliminary

DS11181D-page 1

FEATURES

• Single supply with programming operation down

to 2.5V

• Low power CMOS technology

- 1 mA active current typical

- 5

A standby current (typical) at 3.0V

• x16 memory organization

- 128x16 (93LCS56)

- 256x16 (93LCS66)

• Software write protection of user deﬁned memory

space

• Self timed erase and write cycles

• Automatic ERAL before WRAL

• Power on/off data protection

• Industry standard 3-wire serial I/O

• Device status signal during E/W

• Sequential READ function

• 1,000,000 E/W cycles guaranteed

• Data retention > 200 years

• 8-pin PDIP/SOIC and 14-pin SOIC packages

• Temperature ranges supported

- Commercial (C):

0˚C to +70˚C

- Industrial (I):

-40˚C to +85˚C

BLOCK DIAGRAM

DESCRIPTION

The Microchip Technology Inc. 93LCS56/66 are low volt-

age Serial Electrically Erasable PROMs with memory

capacities of 2K bits/4K bits respectively. A write protect

region of write protected memory. All memory locations

greater than or equal to the address placed in the write

protect register will be protected from any attempted write

or erase operation. It is also possible to protect the

address in the write protect register permanently by using

a one time only instruction (PRDS). Any attempt to alter

data in a register whose address is equal to or greater

than the address stored in the protect register will be

aborted. Advanced CMOS technology makes this device

ideal for low power non-volatile memory applications.

MEMORY

ARRAY

ADDRESS

DECODER

DATA REGISTER

MODE

DECODE

LOGIC

CLOCK

GENERATOR

OUTPUT

BUFFER

CLK

PRE

ADDRESS

COUNTER

93LCS56/66

2K/4K 2.5V Microwire

Serial EEPROM with Software Write Protect

PACKAGE TYPES

93LCS56

93LCS66

93LCS56

93LCS66

93LCS56

93LCS66

SOIC

PRE

CLK

SOIC

PRE

CLK

PRE

CLK

DIP

Microwire is a registered trademark of National Semiconductor Incorporated.

This document was created with FrameMaker 4 0 4

93LCS56/66

DS11181D-page 2

Preliminary

1996 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

Storage temperature ..................................... -65˚C to +150˚C

Ambient temp. with power applied ................ -65˚C to +125˚C

Soldering temperature of leads (10 seconds) ............. +300˚C

ESD protection on all pins................................................4 kV

*Notice:

Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

Chip Select

CLK

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Program Enable

PRE

Protect Register Enable

Power Supply

TABLE 1-2:

DC AND AC ELECTRICAL CHARACTERISTICS

= +2.5V to +6.0V

Commercial(C): Tamb = 0˚C to +70˚C

Industrial (I):

Tamb = -40˚C to +85˚C

Parameter

Symbol

Min

Max

Units

Conditions

High level input voltage

2.0

≥

2.5V

Low level input voltage

-0.3

0.8

≥

2.5V

Low level output voltage

—

0.4

= 2.1 mA; V

= 4.5V

—

0.2

= 100

A; V

= 2.5V

High level output voltage

2.4

—

= -400

A; V

= 4.5V

-0.2

—

= -100

A; V

= 2.5V

Input leakage current

-10

= 0.1V to V

Output leakage current

-10

OUT

= 0.1V to Vcc

Pin capacitance

(all inputs/outputs)

, C

OUT

—

OUT

= 0V (Note 1 & 2)

Tamb = +25˚C; F

CLK

= 1 MHz

Operating current

Write

—

CLK

= 2 MHz; V

= 3.0V (Note 2)

Read

—

500

CLK

= 2 MHz; V

= 6.0V

CLK

= 1 MHz; V

= 3.0V

Standby current

CCS

—

100

CLK = CS = 0V; V

= 6.0V

CLK = CS = 0V; V

= 3.0V

Clock frequency

CLK

—

MHz

≥

4.5V

< 4.5V

Clock high time

CKH

250

—

Clock low time

CKL

250

—

Chip select setup time

CSS

—

Relative to CLK

Chip select hold time

CSH

—

Relative to CLK

Chip select low time

CSL

250

—

PRE setup time

PRES

100

—

Relative to CLK

PE setup time

PES

100

—

Relative to CLK

PRE hold time

PREH

—

Relative to CLK

PE hold time

PEH

500

—

Relative to CLK

Data input setup time

DIS

100

—

Relative to CLK

Data input hold time

DIH

100

—

Relative to CLK

Data output delay time

—

400

CL=100 pF

Data output disable time

—

100

CL=100 pF (Note 2)

Note 1: This parameter is tested at Tamb = 25˚C and F

CLK

= 1 MHz.

2: This parameter is periodically sampled and not 100% tested.

This document was created with FrameMaker 4 0 4

1996 Microchip Technology Inc.

Preliminary

DS11181D-page 3

93LCS56/66

TABLE 1-3:

INSTRUCTION SET FOR 93LCS56*/66

Status valid time

500

CL=100 pF

Program cycle time

ERASE/WRITE mode (Note 3)

ERAL mode

WRAL mode

Endurance

—

cycles

C, Vcc = 5.0V, Block Mode

(Note 4)

3: Typical program cycle time is 4 ms per word.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

93LCS56/66 (x 16 organization)

Instruction SB Opcode

Address

Data In

Data Out

PRE

Comments

READ

A7 - A0

—

D15-D0

Reads data stored in memory, start-

ing at speciﬁed address (.Note).

EWEN

11XXXXXX

—

High-Z

Erase/Write Enable must precede all

programming modes.

ERASE

A7 - A0

—

(RDY/

BSY)

Erase data at speciﬁed address

location if address is unprotected

(Note).

ERAL

10XXXXXX

—

(RDY/

BSY)

Erase all registers to “FF”. Valid only

when Protect Register is cleared.

WRITE

A7 - A0*

D15 - D0

(RDY/

BSY)

Writes register if address is unpro-

tected.

WRAL

01XXXXXX

D15 - D0

(RDY/

BSY)

Writes all registers. Valid only when

Protect Register is cleared.

EWDS

00XXXXXX

—

High-Z

Erase/Write Disable deactivates all

programming instructions.

PRREAD

XXXXXXXX

—

A7-A0

Reads address stored in Protect

PREN

11XXXXXX

—

High-Z

Must immediately precede

PRCLEAR, PRWRITE and PRDS

instructions.

PRCLEAR

11111111

—

(RDY/

BSY)

Clears the Protect Register such that

all data are NOT write-protected.

PRWRITE

A7 - A0*

—

(RDY/

BSY)

Programs address into Protect Reg-

ister. Thereafter, memory addresses

greater than or equal to the address

in Protect Register are write-pro-

tected.

PRDS

00000000

—

(RDY/

BSY)

ONE TIME ONLY instruction after

which the address in the Protect

Note:

Address A7 bit is a “don’t care” on 93LCS56.

TABLE 1-2:

DC AND AC ELECTRICAL CHARACTERISTICS

= +2.5V to +6.0V

Commercial(C): Tamb = 0˚C to +70˚C

Industrial (I):

Tamb = -40˚C to +85˚C

Parameter

Symbol

Min

Max

Units

Conditions

(Continued)

93LCS56/66

DS11181D-page 4

Preliminary

1996 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The 93LCS56/66 is organized as 128/256 registers by

16 bits. Instructions, addresses and write data are

clocked into the DI pin on the rising edge of the clock

(CLK). The DO pin is normally held in a high-Z state

except when reading data from the device, or when

checking the ready/busy status during a programming

operation. The ready/busy status can be veriﬁed during

an Erase/Write operation by polling the DO pin; DO low

indicates that programming is still in progress, while DO

high indicates the device is ready. The DO will enter the

high-Z state on the falling edge of the CS.

2.1

START Condition

The START bit is detected by the device if CS and DI

are both HIGH with respect to the positive edge of CLK

for the ﬁrst time.

Before a START condition is detected, CS, CLK, and DI

may change in any combination (except to that of a

START condition), without resulting in any device oper-

ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,

WRAL, PRREAD, PREN, PRCLEAR, PRWRITE, and

PRDS). As soon as CS is HIGH, the device is no longer

in the standby mode.

An instruction following a START condition will only be

executed if the required amount of opcode, address

and data bits for any particular instruction is clocked in.

After execution of an instruction (i.e., clock in or out of

the last required address or data bit) CLK and DI

become don't care bits until a new start condition is

detected.

2.2

DI/DO

It is possible to connect the Data In and Data Out pins

together. However, with this conﬁguration it is possible

for a “bus conﬂict” to occur during the “dummy zero” that

precedes the READ operation, if A0 is a logic HIGH

level. Under such a condition the voltage level seen at

Data Out is undeﬁned and will depend upon the relative

impedances of Data Out and the signal source driving

A0. The higher the current sourcing capability of A0, the

higher the voltage at the Data Out pin.

2.3

Data Protection

During power-up, all programming modes of operation

are inhibited until V

has reached a level greater than

1.4V. During power-down, the source data protection

circuitry acts to inhibit all programming modes when

has fallen below 1.4V.

The EWEN and EWDS commands give additional pro-

tection against accidentally programming during nor-

mal operation.

After power-up, the device is automatically in the

EWDS mode. Therefore, an EWEN instruction must be

performed before any ERASE or WRITE instruction can

be executed.

2.4

READ

The READ instruction outputs the serial data of the

addressed memory location on the DO pin. A dummy

zero bit precedes the 16 bit output string. The output

data bits will toggle on the rising edge of the CLK and

are stable after the speciﬁed time delay (T

). Sequen-

tial read is possible when CS is held high. The memory

data will automatically cycle to the next register and

output sequentially.

2.5

Erase/Write Enable and Disable

(EWEN, EWDS)

The 93LCS56/66 powers up in the Erase/Write Disable

(EWDS) state. All programming modes must be pre-

ceded by an Erase/Write Enable (EWEN) instruction.

The PE pin MUST be held “high” while loading the

EWEN instruction. Once the EWEN instruction is exe-

cuted, programming remains enabled until an EWDS

instruction is executed or V

is removed from the

device. To protect against accidental data disturb, the

EWDS instruction can be used to disable all Erase/

Write functions and should follow all programming

operations. Execution of a READ instruction is indepen-

dent of both the EWEN and EWDS instructions.

2.6

ERASE

The ERASE instruction forces all data bits of the spec-

iﬁed address to the logical “1” state. CS is brought low

following the loading of the last address bit. This falling

edge of the CS pin initiates the self-timed programming

cycle. The PE pin MUST be latched “high” during load-

ing the ERASE instruction but becomes a “don't care”

after loading the instruction.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (T

CLS

). DO at logical “0” indicates that program-

ming is still in progress. DO at logical “1” indicates that

the register at the speciﬁed address has been erased

and the device is ready for another instruction. ERASE

instruction is valid if speciﬁed address is unprotected.

The ERASE cycle takes 4 ms per word typical.

2.7

WRITE

The WRITE instruction is followed by 16 bits of data

which are written into the speciﬁed address. After the

last data bit is put on the DI pin, CS must be brought low

before the next rising edge of the CLK clock. Both CS

and CLK must be low to initiate the self-timed auto-

erase and programming cycle. The PE pin MUST be

latched “high” while loading the WRITE instruction but

becomes a “don't care” thereafter.

1996 Microchip Technology Inc.

Preliminary

DS11181D-page 5

93LCS56/66

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

CSL

) and before the entire write cycle is complete. DO

at logical “0” indicates that programming is still in

progress. DO at logical “1” indicates that the register at

the speciﬁed address has been written with the data

speciﬁed and the device is ready for another instruc-

tion. WRITE instruction is valid only if speciﬁed address

is unprotected.

The WRITE cycle takes 4 ms per word typical.

2.8

Erase All (ERAL)

The ERAL instruction will erase the entire memory

array to the logical “1”. The ERAL cycle is identical to

the ERASE cycle except for the different opcode. The

ERAL cycle is completely self-timed and commences at

the falling edge of the CS. PE pin MUST be held “high”

while loading the instruction but becomes “don't care”

thereafter. Clocking of the CLK pin is not necessary

after the device has entered the self clocking mode.

The ERAL instruction is guaranteed at V

= 4.5 to 6V

and valid only when Protect Register is cleared.

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (T

CSL

) and before the entire write cycle is complete.

The ERAL cycle takes 15 ms maximum (8 ms typical).

2.9

Write All (WRAL)

The WRAL instruction will write the entire memory array

with the data speciﬁed in the command. The WRAL

cycle is completely self-timed and commences at the

falling edge of the CS. PE pin MUST be held “high”

while loading the instruction but becomes “don't care”

thereafter. Clocking of the CLK pin is not necessary

after the device has entered the self clocking mode.

The WRAL command does include an automatic ERAL

cycle for the device. Therefore, the WRAL instruction

does not require an ERAL instruction but the chip must

be in the EWEN status. The WRAL instruction is guar-

anteed at V

= 4.5 to 6V and valid only when Protect

The DO pin indicates the READY/BUSY status of the

device if CS is brought high after a minimum of 250 ns

low (T

CSL

The WRAL cycle takes 30 ms maximum (16 ms typical).

Note:

In order to execute either READ, EWEN,

ERAL, WRITE, WRAL, or EWDS instruc-

tions, the Protect Register Enable (PRE)

pin must be held LOW.

2.10

Protect Register Read (PRREAD)

The Protect Register Read (PRREAD) instruction out-

puts the address stored in the Protect Register on the

DO pin. The PRE pin MUST be held HIGH when load-

ing the instruction and remains HIGH until CS goes

LOW. A dummy zero bit precedes the 8-bit output

string. The output data bits in the memory Protect Reg-

ister will toggle on the rising edge of the CLK as in the

READ mode.

2.11

Protect Register Enable (PREN)

The Protect Register Enable (PREN) instruction is used

to enable the PRCLEAR, PRWRITE, and PRDS

modes. Before the PREN mode can be entered, the

device must be in the EWEN mode. Both PRE and PE

pins MUST be held “high” while loading the instruction.

The PREN instruction MUST immediately precede a

PRCLEAR, PRWRITE, or PRDS instruction.

2.12

Protect Register Clear (PRCLEAR)

The Protect Register Clear (PRCLEAR) instruction

clears the address stored in the Protect Register and,

therefore, enables all registers for programming

instructions such as ERASE, ERAL, WRITE, and

WRAL. The PRE and PE pin MUST be held HIGH when

loading the instruction. Thereafter, PRE and PE pins

become “don't care”. A PREN instruction must immedi-

ately precede a PRCLEAR instruction.

2.13

Protect Register Write (PRWRITE)

The Protect Register Write (PRWRITE) instruction

writes into the Protect Register the address of the ﬁrst

cuted, all registers whose memory addresses are

greater than or equal to the address pointer speciﬁed in

the Protect register are protected from any program-

ming instructions. Note that a PREN instruction must

be executed before a PRWRITE instruction and, the

Protect Register must be cleared (by a PRCLEAR

instruction) before executing the PRWRITE instruction.

The PRE and PE pins MUST be held HIGH while load-

ing PRWRITE instruction. After the instruction is

loaded, they become “don't care”.

2.14

Protect Register Disable (PRDS)

The Protect Register Disable (PRDS) instruction is a

ONE TIME ONLY instruction to permanently set the

address speciﬁed in the Protect Register. Any attempts

to change the address pointer will be aborted. The PRE

and PE pins MUST be held HIGH while loading PRDS

instruction. After the instruction is loaded, they become

“don't care”. Note that a PREN instruction must be exe-

cuted before a PRDS instruction.