©
1997 Microchip Technology Inc.
Preliminary
DS30235F-page 1
Devices included in this data sheet:
Referred to collectively as PIC16C62X(A).
• PIC16C620
• PIC16C620A
• PIC16C621
• PIC16C621A
• PIC16C622
• PIC16C622A
High Performance RISC CPU:
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
• Interrupt capability
• 16 special function hardware registers
• 8-level deep hardware stack
• Direct, Indirect and Relative addressing modes
Peripheral Features:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(V
REF
) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Device
Program
Memory
Data
Memory
PIC16C620
512
80
PIC16C620A
512
80
PIC16C621
1K
80
PIC16C621A
1K
80
PIC16C622
2K
128
PIC16C622A
2K
128
Pin Diagrams
Special Microcontroller Features (cont’d)
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Serial in-circuit programming (via two pins)
• Four user programmable ID locations
CMOS Technology:
• Low-power, high-speed CMOS EPROM technology
• Fully static design
• Wide operating voltage range
- PIC16C62X - 2.5V to 6.0V
- PIC16C62XA - 3.0V to 5.5V
• Commercial, industrial and extended tempera-
ture range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15
µ
A typical @ 3.0V, 32 kHz
- < 1.0
µ
A typical standby current @ 3.0V
RA1/AN1
RA0/AN0
OSC2/CLKOUT
V
DD
RB7
RB6
RB5
RB4
OSC1/CLKIN
RA2/AN2/V
REF
RA3/AN3
MCLR
V
SS
RB0/INT
RB1
RB2
RB3
RA4/T0CKI
PIC16C62X(A)
RA1/AN1
RA0/AN0
OSC2/CLKOUT
V
DD
RB7
RB6
RB5
RB4
OSC1/CLKIN
RA2/AN2/V
REF
RA3/AN3
MCLR
V
SS
V
SS
RB0/INT
RB1
RB2
RA4/T0CKI
PIC16C62X(A)
RB3
RB3
V
DD
PDIP, SOIC, Windowed CERDIP
SSOP
2
3
4
5
6
7
8
9
10
•1
2
3
4
5
6
7
8
9
•1
19
18
16
15
14
13
12
11
17
18
17
15
14
13
12
11
10
16
20
EPROM-Based 8-Bit CMOS Microcontroller
PIC16C62X(A)
PIC16C62X(A)
DS30235F-page 2
Preliminary
©
1997 Microchip Technology Inc.
Device Differences
Note 1:
If you change from this device to another device, please verify oscillator characteristics in your application.
Device
Voltage
Range
Oscillator
Process
Technology
(Microns)
PIC16C620
2.5 - 6.0
See Note 1
0.9
PIC16C621
2.5 - 6.0
See Note 1
0.9
PIC16C622
2.5 - 6.0
See Note 1
0.9
PIC16C620A
3.0 - 5.5
See Note 1
0.7
PIC16C621A
3.0 - 5.5
See Note 1
0.7
PIC16C622A
3.0 - 5.5
See Note 1
0.7
©
1997 Microchip Technology Inc.
Preliminary
DS30235F-page 3
PIC16C62X(A)
Table of Contents
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. To this end, we recently con-
verted to a new publishing software package which we believe will enhance our entire documentation process and
product. As in any conversion process, information may have accidently been altered or deleted. We have spent an
exceptional amount of time to ensure that these documents are correct. However, we realize that we may have
missed a few things. If you find any information that is missing or appears in error from the previous version of this
data sheet (PIC16C62X(A) Data Sheet, Literature Number DS30235F), please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
PIC16C62X(A)
DS30235F-page 4
Preliminary
©
1997 Microchip Technology Inc.
NOTES:
©
1997 Microchip Technology Inc.
Preliminary
DS30235F-page 5
PIC16C62X(A)
1.0
GENERAL DESCRIPTION
The PIC16C62X(A) are 18 and 20 Pin EPROM-based
members of the versatile PICmicro™ family of low-cost,
high-performance, CMOS, fully-static, 8-bit
microcontrollers.
All PICmicro™ microcontrollers employ an advanced
RISC architecture. The PIC16C62X(A) have enhanced
core features, eight-level deep stack, and multiple inter-
nal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with the separate
8-bit wide data. The two-stage instruction pipeline
allows all instructions to execute in a single-cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
PIC16C62X(A) microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C620(A) and PIC16C621(A) have 80 bytes
of RAM. The PIC16C622(A) has 128 bytes of RAM.
Each device has 13 I/O pins and an 8-bit timer/counter
with an 8-bit programmable prescaler. In addition, the
PIC16C62X(A) adds two analog comparators with a
programmable on-chip voltage reference module. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers, threshold detectors, white goods
controllers,
etc).
PIC16C62X(A) devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power con-
sumption. There are four oscillator options, of which the
single pin RC oscillator provides a low-cost solution,
the LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power savings.
The user can wake up the chip from SLEEP through
several external and internal interrupts and reset.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
mid-range microcontroller families.
A simplified block diagram of the PIC16C62X(A) is
The PIC16C62X(A) series fit perfectly in applications
ranging from battery chargers to low-power remote
sensors. The EPROM technology makes customization
of application programs (detection levels, pulse gener-
ation, timers, etc.) extremely fast and convenient. The
small footprint packages make this microcontroller
series perfect for all applications with space limitations.
Low-cost, low-power, high-performance, ease of use
and I/O flexibility make the PIC16C62X(A) very versa-
tile.
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X can be easily ported to
PIC16C62X(A) family of devices (Appendix B). The
PIC16C62X(A) family fills the niche for users wanting to
migrate up from the PIC16C5X family and not needing
various peripheral features of other members of the
PIC16XX mid-range microcontroller family.
1.2
Development Support
The PIC16C62X(A) family is supported by a full-fea-
tured macro assembler, a software simulator, an in-cir-
cuit emulator, a low-cost development programmer and
a full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
PIC16C62X(A)
DS30235F-page 6
Preliminary
©
1997 Microchip Technology Inc.
TABLE 1-1:
PIC16C62X(A) FAMILY OF DEVICES
PIC16C620
PIC16C620A
PIC16C621
PIC16C621A
PIC16C622
PIC16C622A
Clock
Maximum Frequency
of Operation (MHz)
20
20
20
20
20
20
Memory
EPROM Program
Memory
(x14 words)
512
512
1K
1K
2K
2K
Data Memory (bytes)
80
80
80
80
128
128
Peripherals
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
Comparators(s)
2
2
2
2
2
2
Internal Reference
Voltage
Yes
Yes
Yes
Yes
Yes
Yes
Features
Interrupt Sources
4
4
4
4
4
4
I/O Pins
13
13
13
13
13
13
Voltage Range (Volts)
2.5-6.0
3.0-5.5
2.5-6.0
3.0-5.5
2.5-6.0
3.0-5.5
Brown-out Reset
Yes
Yes
Yes
Yes
Yes
Yes
Packages
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C62X(A) Family devices use serial programming with clock pin RB6 and data pin RB7.
©
1997 Microchip Technology Inc.
Preliminary
DS30235F-page 7
PIC16C62X(A)
2.0
PIC16C62X(A) DEVICE
VARIETIES
A variety of frequency ranges and packaging options are
available. Depending on application and production
requirements the proper device option can be selected
using the information in the PIC16C62X(A) Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of the
data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART
®
and PRO
MATE
®
programmers both support programming of the
PIC16C62X(A).
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are identical to the OTP devices
but with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more details.
2.4
Serialized
Quick-Turnaround-Production
(SQTP
SM
) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
PIC16C62X(A)
DS30235F-page 8
Preliminary
©
1997 Microchip Technology Inc.
NOTES:
©
1997 Microchip Technology Inc.
Preliminary
DS30235F-page 9
PIC16C62X(A)
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C62X(A) family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C62X(A) uses a Harvard architecture,
in which, program and data are accessed from sepa-
rate memories using separate busses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit
wide data word. Instruction opcodes are 14-bits wide
making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a sin-
gle-cycle (200 ns @ 20 MHz) except for program
branches.
The PIC16C620(A) addresses 512 x 14 on-chip pro-
gram memory. The PIC16C621(A) addresses 1K x 14
program memory. The PIC16C622(A) addresses 2K x
14 program memory. All program memory is internal.
The PIC16C62X(A) can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C62X(A) have an orthog-
onal (symmetrical) instruction set that makes it possi-
ble to carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C62X(A) simple yet efficient. In addition, the
learning curve is reduced significantly.
The PIC16C62X(A) devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W
register).
The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the
SUBLW
and
SUBWF
instructions for examples.
PIC16C62X(A)
DS30235F-page 10
Preliminary
©
1997 Microchip Technology Inc.
FIGURE 3-1:
BLOCK DIAGRAM
EPROM
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr
7
RAM Addr
(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
V
DD
, V
SS
Voltage
Brown-out
Reset
Note 1:
Higher order bits are from the STATUS register.
Device
Program Memory
Data Memory
(RAM)
PIC16C620
PIC16C620A
PIC16C621
PIC16C621A
PIC16C622
PIC16C622A
512 x 14
512 x 14
1K x 14
1KX14
2K x 14
2KX14
80 x 8
80X8
80 x 8
80X8
128 x 8
128X8
8
3
TMR0
I/O Ports
PORTB
Comparator
RA3/AN3
RA2/AN2/V
REF
RA1/AN1
RA0/AN0
Reference
RA4/T0CKI
+
-
+
-
©
1997 Microchip Technology Inc.
Preliminary
DS30235F-page 11
PIC16C62X(A)
TABLE 3-1:
PIC16C62X(A) PINOUT DESCRIPTION
Name
DIP
SOIC
Pin #
SSOP
Pin #
I/O/P
Type
Buffer
Type
Description
OSC1/CLKIN
16
18
I
ST/CMOS Oscillator crystal input/external clock source input.
OSC2/CLKOUT
15
17
O
—
Oscillator crystal output. Connects to crystal or resonator
in crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/V
PP
4
4
I/P
ST
Master clear (reset) input/programming voltage input.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0
17
19
I/O
ST
Analog comparator input
RA1/AN1
18
20
I/O
ST
Analog comparator input
RA2/AN2/V
REF
1
1
I/O
ST
Analog comparator input or V
REF
output
RA3/AN3
2
2
I/O
ST
Analog comparator input /output
RA4/T0CKI
3
3
I/O
ST
Can be selected to be the clock input to the Timer0
timer/counter or a comparator output. Output is open
drain type.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT
6
7
I/O
TTL/ST
(1)
RB0/INT can also be selected as an external
interrupt pin.
RB1
7
8
I/O
TTL
RB2
8
9
I/O
TTL
RB3
9
10
I/O
TTL
RB4
10
11
I/O
TTL
Interrupt on change pin.
RB5
11
12
I/O
TTL
Interrupt on change pin.
RB6
12
13
I/O
TTL/ST
(2)
Interrupt on change pin. Serial programming clock.
RB7
13
14
I/O
TTL/ST
(2)
Interrupt on change pin. Serial programming data.
V
SS
5
5,6
P
—
Ground reference for logic and I/O pins.
V
DD
14
15,16
P
—
Positive supply for logic and I/O pins.
Legend:
O = output
I/O = input/output
P = power
— = Not used
I = Input
ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
PIC16C62X(A)
DS30235F-page 12
Preliminary
©
1997 Microchip Technology Inc.
3.1
Clocking Scheme/Instruction Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
3.2
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g.,
GOTO
)
then two cycles are required to complete the instruction
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1. MOVLW 55h
Fetch 1
Execute 1
2. MOVWF PORTB
Fetch 2