c72.book

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Key Reference Manual Features

PIC16C72

PIC16CR72

Operating Frequency

DC - 20MHz

Resets

POR, PWRT, OST, BOR

Program Memory - (14-bit words)

2K (EPROM)

2K (ROM)

Data Memory - RAM (8-bit bytes)

128

Interrupts

I/O Ports

PortA, PortB, PortC

Timers

Timer0, Timer1, Timer2

Capture/Compare/PWM Modules

Serial Communications

Basic SSP

SSP

8-Bit A/D Converter

5 channels

Instruction Set (No. of Instructions)

PIC16C72 Series

1998 Microchip Technology Inc.

Preliminary

DS39016A-page 3

1.0

DEVICE OVERVIEW

This document contains device-speciﬁc information for

the operation of the PIC16C72 device. Additional infor-

mation may be found in the PICmicro™ Mid-Range

MCU Reference Manual (DS33023) which may be

downloaded from the Microchip website. The Refer-

ence Manual should be considered a complementary

document to this data sheet, and is highly recom-

mended reading for a better understanding of the

device architecture and operation of the peripheral

modules.

The PIC16C72 belongs to the Mid-Range family of the

PICmicro devices. A block diagram of the device is

shown in Figure 1-1.

The program memory contains 2K words which trans-

late to 2048 instructions, since each 14-bit program

memory word is the same width as each device instruc-

tion. The data memory (RAM) contains 128 bytes.

There are also 22 I/O pins that are user-conﬁgurable on

a pin-to-pin basis. Some pins are multiplexed with other

device functions. These functions include:

• External interrupt

• Change on PORTB interrupt

• Timer0 clock input

• Timer1 clock/oscillator

• Capture/Compare/PWM

• A/D converter

• SPI/I

Table 1-1 details the pinout of the device with descrip-

tions and details for each pin.

FIGURE 1-1:

PIC16C72/CR72 BLOCK DIAGRAM

EPROM/

Program

Memory

2K x 14

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

128 x 8

Direct Addr

RAM Addr

(1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

, V

Timer0

A/D

Synchronous

Serial Port

PORTA

PORTB

PORTC

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC6

RC7

Brown-out

Reset

Note 1:

Higher order bits are from the STATUS register.

CCP1

Timer1

Timer2

RA4/T0CKI

RA5/SS/AN4

RA3/AN3/V

REF

RA2/AN2

RA1/AN1

RA0/AN0

ROM

PIC16C72 Series

DS39016A-page 4

Preliminary

1998 Microchip Technology Inc.

TABLE 1-1

PIC16C72/CR72 PINOUT DESCRIPTION

Pin Name

Pin#

I/O/P

Type

Buffer

Type

Description

OSC1/CLKIN

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

—

Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which

has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR/V

I/P

Master clear (reset) input or programming voltage input. This pin is an

active low reset to the device.

PORTA is a bi-directional I/O port.

RA0/AN0

I/O

TTL

RA0 can also be analog input0.

RA1/AN1

I/O

TTL

RA1 can also be analog input1.

RA2/AN2

I/O

TTL

RA2 can also be analog input2.

RA3/AN3/V

REF

I/O

TTL

RA3 can also be analog input3 or analog reference voltage

RA4/T0CKI

I/O

RA4 can also be the clock input to the Timer0 module. Output is

open drain type.

RA5/SS/AN4

I/O

TTL

RA5 can also be analog input4 or the slave select for the

synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs.

RB0/INT

I/O

TTL/ST

(1)

RB0 can also be the external interrupt pin.

RB1

I/O

TTL

RB2

I/O

TTL

RB3

I/O

TTL

RB4

I/O

TTL

Interrupt on change pin.

RB5

I/O

TTL

Interrupt on change pin.

RB6

I/O

TTL/ST

(2)

Interrupt on change pin. Serial programming clock.

RB7

I/O

TTL/ST

(2)

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI

I/O

RC0 can also be the Timer1 oscillator output or Timer1 clock

input.

RC1/T1OSI

I/O

RC1 can also be the Timer1 oscillator input.

RC2/CCP1

I/O

RC2 can also be the Capture1 input/Compare1 output/PWM1

output.

RC3/SCK/SCL

I/O

RC3 can also be the synchronous serial clock input/output for both

SPI and I

C modes.

RC4/SDI/SDA

I/O

RC4 can also be the SPI Data In (SPI mode) or

data I/O (I

C mode).

RC5/SDO

I/O

RC5 can also be the SPI Data Out (SPI mode).

RC6

I/O

RC7

I/O

8, 19

—

Ground reference for logic and I/O pins.

—

Positive supply for logic and I/O pins.

Legend: I = input

O = output

I/O = input/output

P = power

— = Not used

TTL = TTL input

ST = Schmitt Trigger input

Note 1:

This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

This buffer is a Schmitt Trigger input when used in serial programming mode.

This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise

PIC16C72 Series

1998 Microchip Technology Inc.

Preliminary

DS39016A-page 5

2.0

MEMORY ORGANIZATION

There are two memory blocks in PIC16C72 Series

devices. These are the program memory and the data

memory. Each block has its own bus, so that access to

both blocks can occur during the same oscillator cycle.

The data memory can further be broken down into the

general purpose RAM and the Special Function

Registers (SFRs). The operation of the SFRs that

control the “core” are described here. The SFRs used

to control the peripheral modules are described in the

section discussing each individual peripheral module.

Additional information on device memory may be found

in the PICmicro™ Mid-Range Reference Manual,

DS33023.

2.1

Program Memory Organization

PIC16C72 Series devices have a 13-bit program

counter capable of addressing a 2K x 14 program

memory space. The address range for this program

memory is 0000h - 07FFh. Accessing a location above

the physically implemented address will cause a wrap-

around.

The reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK

PC<12:0>

0000h

0004h

0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0800h

User Memor

Space

PIC16C72 Series

DS39016A-page 6

Preliminary

1998 Microchip Technology Inc.

2.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 and RP0 are the

bank select bits.

= 00

→

Bank0

= 01

→

Bank1

= 10

→

Bank2 (not implemented)

= 11

→

Bank3 (not implemented)

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM.

All implemented banks contain special function regis-

ters. Some “high use” special function registers from

one bank may be mirrored in another bank for code

reduction and quicker access (ex; the STATUS register

is in Bank 0 and Bank 1).

2.2.1

GENERAL PURPOSE REGISTER FILE

The register ﬁle can be accessed either directly or indi-

rectly through the File Select Register FSR

(Section

2.5).

FIGURE 2-2:

REGISTER FILE MAP

RP1*

RP0

(STATUS<6:5>)

Maintain this bit clear to ensure upward com-

patibility with future products.

INDF

(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

ADRES

ADCON0

INDF

(1)

OPTION

PCL

STATUS

FSR

TRISA

TRISB

TRISC

PCLATH

INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

ADCON1

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h

A0h

General

Purpose

General

Purpose

7Fh

FFh

Bank 0

Bank 1

File

Address

BFh

C0h

Unimplemented data memory locations, read as '0'.

Note 1:

Not a physical register.

File

Address

PIC16C72 Series

1998 Microchip Technology Inc.

Preliminary

DS39016A-page 7

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

The special function registers can be classiﬁed into two

sets (core and peripheral). Those registers associated

with the “core” functions are described in this section,

and those related to the operation of the peripheral fea-

tures are described in the section of that peripheral fea-

ture.

TABLE 2-1

SPECIAL FUNCTION REGISTER SUMMARY

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on all

other resets

(3)

Bank 0

00h

(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h

(1)

PCL

Program Counter's (PC) Least Signiﬁcant Byte

0000 0000

03h

(1)

STATUS

IRP

(4)

RP1

(4)

RP0

0001 1xxx

000q quuu

04h

(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

—

PORTA Data Latch when written: PORTA pins when read

--0x 0000

--0u 0000

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

PORTC

PORTC Data Latch when written: PORTC pins when read

xxxx xxxx

uuuu uuuu

08h

—

Unimplemented

—

09h

—

Unimplemented

—

0Ah

(1,2)

PCLATH

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

0Bh

(1)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

—

ADIF

—

SSPIF

CCP1IF

TMR2IF

TMR1IF

-0-- 0000

0Dh

—

Unimplemented

—

0Eh

TMR1L

Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

0Fh

TMR1H

Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx

uuuu uuuu

10h

T1CON

—

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

--00 0000

--uu uuuu

11h

TMR2

Timer2 module’s register

0000 0000

12h

T2CON

—

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

13h

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx

uuuu uuuu

14h

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

15h

CCPR1L

Capture/Compare/PWM Register (LSB)

xxxx xxxx

uuuu uuuu

16h

CCPR1H

Capture/Compare/PWM Register (MSB)

xxxx xxxx

uuuu uuuu

17h

CCP1CON

—

CCP1X

CCP1Y

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

18h-1Dh

—

Unimplemented

—

1Eh

ADRES

A/D Result Register

xxxx xxxx