©
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 1
M
24LC024/24LC025
FEATURES
• Single supply with operation from 2.5 to 5.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
• Organized as a single block of 128 bytes (256 x 8)
• Hardware write protection for entire array
(24LC024)
• 2-wire serial interface bus, I
2
C compatible
• 100kHz and 400kHz compatibility
• Page-write buffer for up to 16 bytes
• Self-timed write cycle (including auto-erase)
• 3.5 ms typical write cycle time for page write
• Address lines allow up to eight devices on bus
• 10,000,000 erase/write cycles guaranteed
• ESD protection > 4,000V
• Data retention > 200 years
• 8-pin PDIP, SOIC or TSSOP packages
• Available for extended temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24LC024/24LC025 is a
2K bit Serial Electrically Erasable PROM with a voltage
range of 2.5V to 5.5V. The device is organized as a
single block of 256 x 8-bit memory with a 2-wire serial
interface. Low current design permits operation with
typical standby and active currents of only 10
µ
A and 1
mA respectively. The device has a page-write capability
for up to 16 bytes of data. Functional address lines
allow the connection of up to eight 24LC024/24LC025
devices on the same bus for up to 16K bits of contigu-
ous EEPROM memory. The device is available in the
standard 8-pin PDIP, 8-pin SOIC (150 mil), and TSSOP
packages.
PACKAGE TYPES
BLOCK DIAGRAM
- Commercial (C):
0
°
C to
+70
°
C
- Industrial (I):
-40
°
C to
+85
°
C
PDIP/SOIC
TSSOP
A0
A1
A2
Vss
Vcc
WP*
SCL
SDA
24LC024
25LC025
24LC024
24LC025
1
2
3
4
8
7
6
5
A0
A1
A2
V
SS
V
CC
WP*
SCL
SDA
1
2
3
4
8
7
6
5
*WP pin available only on 24LC024. This
pin has no internal connection on 24LC025
I/O
Control
Logic
Memory
Control
Logic
XDEC
HV Generator
EEPROM
Array
Write Protect
Circuitry
YDEC
V
CC
V
SS
SENSE AMP
R/W CONTROL
SDA SCL
A0 A1 A2
WP*
*WP pin available only on 24LC024. This
pin has no internal connection on 24LC025
2K 2.5V I
2
C
™
Serial EEPROM
24LC024/24LC025
DS21210A-page 2
Preliminary
©
1997 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
........................................................................ 7.0V
All inputs and outputs w.r.t. V
SS
...... -0.6V to V
CC
+1.0V
Storage temperature ...........................-65˚C to +150˚C
Ambient temp. with power applied.......-65˚C to +125˚C
Soldering temperature of leads (10 seconds) ...+300˚C
ESD protection on all pins
......................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
Name
Function
V
SS
SDA
SCL
V
CC
A0, A1, A2
WP
NC
Ground
Serial Data
Serial Clock
+2.5V to 5.5V Power Supply
Chip Selects
Hardware Write Protect (24LC024)
No internal connection
TABLE 1-2:
DC CHARACTERISTICS
All parameters apply across the speci-
fied operating ranges unless otherwise
noted.
V
CC
= +2.5V to +5.5V
Commercial (C):
Tamb = 0
°
C to +70
°
C
Industrial (I):
Tamb = -40
°
C to +85
°
C
Parameter
Symbol
Min.
Max.
Units
Conditions
SCL and SDA pins:
High level input voltage
V
IH
0.7 V
CC
V
Low level input voltage
V
IL
0.3 V
CC
V
Hysteresis of Schmitt trigger inputs
V
HYS
0.05 V
CC
—
V
(Note)
Low level output voltage
V
OL
0.40
V
I
OL
= 3.0 mA, V
CC
= 4.5V
I
OL
= 2.1 mA, V
CC
= 2.5V
Input leakage current
I
LI
-10
10
µ
A
V
IN
= 0.1V to 5.5V, WP = Vss
Output leakage current
I
LO
-10
10
µ
A
V
OUT
= 0.1V to 5.5V
Pin capacitance (all inputs/outputs)
C
IN
, C
OUT
—
10
pF
V
CC
= 5.0V (Note)
Tamb = 25
°
C, f = 1 MHz
Operating current
I
CC
Read
—
1
mA
V
CC
= 5.5V, SCL = 400 kHz
I
CC
Write
—
3
mA
V
CC
= 5.5V
Standby current
I
CCS
—
50
µ
A
V
CC
= 5.5V, SDA = SCL = V
CC
A0, A1, A2 = Vss
Note
: This parameter is periodically sampled and not 100% tested.
24LC024/24LC025
©
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 3
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING DATA
All parameters apply across the specified operat-
ing ranges unless otherwise noted.
Vcc = 2.5V to 5.5V
Commercial (C):
Tamb = 0
°
C to +70
°
C
Industrial (I):
Tamb = -40
°
C to +85
°
C
Parameter
Symbol
Vcc = 2.5V - 5.5V
STD MODE
Vcc = 4.5V - 5.5V
FAST MODE
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
F
CLK
—
100
—
400
kHz
Clock high time
T
HIGH
4000
—
600
—
ns
Clock low time
T
LOW
4700
—
1300
—
ns
SDA and SCL rise time
T
R
—
1000
—
300
ns
SDA and SCL fall time
T
F
—
300
—
300
ns
START condition hold time
T
HD
:
STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
START condition setup time
T
SU
:
STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—
0
—
ns
Data input setup time
T
SU
:
DAT
250
—
100
—
ns
STOP condition setup time
T
SU
:
STO
4000
—
600
—
ns
Output valid from clock
T
AA
—
3500
—
900
ns
Bus free time
T
BUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
minimum to V
IL
maximum
T
OF
—
250
20 +0.1
C
B
250
ns
(Note 1), C
B
≤
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
—
50
—
50
ns
Write cycle time
T
WC
—
10
—
10
ms
Byte or Page mode
Endurance
10M
—
10M
—
cycles 25
°
C, V
CC
= 5.0V, Block
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:
The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide improved noise
spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
SCL
SDA
IN
T
SU
:
STA
SDA
OUT
T
HD
:
STA
T
LOW
T
HIGH
T
R
T
BUF
T
AA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
SP
T
F
24LC024/24LC025
DS21210A-page 4
Preliminary
©
1997 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
2.1
SDA Serial Data
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
Ω
for 100 kHz, 2 k
Ω
for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are reserved
for indicating the START and STOP conditions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
A0, A1, A2
The levels on these inputs are compared with the cor-
responding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24LC024/24LC025 devices may be con-
nected to the same bus by using different chip select bit
combinations. These inputs must be connected to
either V
CC
or V
SS
.
2.4
WP (24LC024 only)
This is the hardware write protect pin. It must be tied to
V
CC
or V
SS
. If tied to Vcc, the hardware write protection
is enabled. If the WP pin is tied to Vss the hardware
write protection is disabled. Note that the WP pin is
available only on the 24LC024. This pin is not internally
connected on the 24LC025.
2.5
Noise Protection
The 24LC024/24LC025 employs a V
CC
threshold
detector circuit which disables the internal erase/write
logic if the V
CC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
3.0
FUNCTIONAL DESCRIPTION
The 24LC024/24LC025 supports a bi-directional 2-wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24LC024/24LC025 works as slave. Both master and
slave can operate as transmitter or receiver but the
master device determines which mode is activated.
24LC024/24LC025
©
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 5
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
4.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
4.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
4.5
Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
FIGURE 4-2:
ACKNOWLEDGE TIMING
Note:
The 24LC024/24LC025 does not generate
any acknowledge bits if an internal pro-
gramming cycle is in progress.
(A)
(B)
(C)
(D)
(A)
(C)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
9
8
7
6
5
4
3
2
1
1
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
Data from transmitter
SDA
Acknowledge
Bit
24LC024/24LC025
DS21210A-page 6
Preliminary
©
1997 Microchip Technology Inc.
5.0
DEVICE ADDRESSING
A control byte is the first byte received following the
control byte consists of a four bit control code; for the
24LC024/24LC025 this is set as 1010 binary for read
and write operations. The next three bits of the control
byte are the chip select bits (A2, A1, A0). The chip
select bits allow the use of up to eight 24LC024/
24LC025 devices on the same bus and are used to
select which device is accessed. The chip select bits in
the control byte must correspond to the logic levels on
the corresponding A2, A1, and A0 pins for the device to
respond. These bits are in effect the three most signifi-
cant bits of the word address.
The last bit of the control byte defines the operation to
be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. Following the start condition, the 24LC024/
24LC025 monitors the SDA bus checking the control
byte being transmitted. Upon receiving a 1010 code
and appropriate chip select bits, the slave device out-
puts an acknowledge signal on the SDA line. Depend-
ing on the state of the R/W bit, the 24LC024/24LC025
will select a read or write operation.
FIGURE 5-1:
CONTROL BYTE FORMAT
5.1
Contiguous Addressing Across
Multiple Devices
The chip select bits A2, A1, A0 can be used to expand
the contiguous address space for up to 16K bits by add-
ing up to eight 24LC024/24LC025 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A8, A1 as address bit A9, and A2 as
address bit A10. It is not possible to sequentially read
across device boundaries.
1
0
1
0
A2
A1
A0
S
ACK
R/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
24LC024/24LC025
©
1997 Microchip Technology Inc.
Preliminary
DS21210A-page 7
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the start signal from the master, the device
code(4 bits), the chip select bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. The device will acknowledge this
control byte during the ninth clock pulse. The next byte
transmitted by the master is the word address and will
be written into the address pointer of the 24LC024/
24LC025. After receiving another acknowledge signal
from the 24LC024/24LC025 the master device will
transmit the data word to be written into the addressed
memory location. The 24LC024/24LC025 acknowl-
edges again and the master generates a stop condi-
tion. This initiates the internal write cycle, and during
this time the 24LC024/24LC025 will not generate
to write to the protected portion of the array when the
hardware write protection (24LC024 only) has been
enabled, the device will acknowledge the command but
no data will be written. The write cycle time must be
observed even if the write protection is enabled.
6.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC024/24LC025 in the
same way as in a byte write. But instead of generating
a stop condition, the master transmits up to 15 addi-
tional data bytes to the 24LC024/24LC025 which are
temporarily stored in the on-chip page buffer and will be
written into the memory after the master has transmit-
ted a stop condition. After the receipt of each word, the
four lower order address pointer bits are internally
incremented by one. The higher order four bits of the
word address remains constant. If the master should
transmit more than 16 bytes prior to generating the stop
condition, the address counter will roll over and the pre-
viously received data will be overwritten. As with the
byte write operation, once the stop condition is received
an internal write cycle will begin (Figure 6-2). If an
attempt is made to write to the protected portion of the
array when the hardware write protection has been
enabled, the device will acknowledge the command but
no data will be written. The write cycle time must be
observed even if the write protection is enabled.
6.3
WRITE PROTECTION
The WP pin (available on 24LC024 only) must be tied
to V
CC
or V
SS
. If tied to V
CC
, the entire array will be write
protected. If the WP pin is tied to V
SS
, then write oper-
ations to all address locations are allowed.
FIGURE 6-1:
BYTE WRITE
FIGURE 6-2:
PAGE WRITE
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS
DATA
A
C
K
A
C
K
A
C
K
S
P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
CONTROL
BYTE
WORD
ADDRESS (n)
DATA n
DATA n + 15
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DATA n +1
24LC024/24LC025
DS21210A-page 8
Preliminary
©
1997 Microchip Technology Inc.
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be