©
1996 Microchip Technology Inc.
DS21127B-page 1
FEATURES
• Completely implements DDC1
™
/DDC2
™
interface for monitor identification
• Hardware write-protect pin
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10
µ
A standby current typical at 5.5V
• 2-wire serial interface bus, I
2
C
™
compatible (SCL)
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
(SCL)
• 10,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24LCS21 is a
128 x 8-bit dual-mode Electrically Erasable PROM.
This device is designed for use in applications requiring
storage and serial transmission of configuration and
control information. Two modes of operation have been
implemented: Transmit Only Mode and bi-directional
Mode. Upon power-up, the device will be in the Transmit
Only Mode, sending a serial bit stream of the entire
memory array contents, clocked by the VCLK pin. A
valid high to low transition on the SCL pin will cause the
device to enter the bi-directional Mode, with byte select-
able read/write capability of the memory array in stan-
dard I
2
C protocol.
The 24LCS21 also enables the user to write-protect the
entire memory contents using its write-protect pin. The
24LCS21 is available in a standard 8-pin PDIP and
SOIC package in both commercial and industrial
temperature ranges.
- Commercial (C):
0
°
C to +70
°
C
- Industrial (I)
-40
°
C to +85
°
C
PACKAGE TYPES
BLOCK DIAGRAM
24LCS21
SOIC
1
2
3
4
8
7
6
5
V
CC
VCLK
SCL
SDA
NC
NC
WP
V
SS
24LCS21
PDIP
1
2
3
4
8
7
6
5
V
CC
VCLK
SCL
SDA
NC
NC
WP
V
SS
I/O
CONTROL
LOGIC
EEPROM
ARRAY
PAGE LATCHES
HV GENERATOR
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
XDEC
YDEC
V
CC
V
SS
SDA SCL
VCLK
WP
24LCS21
1K 2.5V Dual Mode I
2
C
™
Serial EEPROM
DDC is a trademark of the Video Electronics Standards Association.
I
2
C is a trademark of Philips Corporation.
This document was created with FrameMaker 4 0 4
24LCS21
DS21127B-page 2
©
1996 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
...................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature .....................................-65
°
C to +150
°
C
Ambient temp. with power applied ................-65
°
C to +125
°
C
Soldering temperature of leads (10 seconds) ............. +300
°
C
ESD protection on all pins
..................................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
Name
Function
WP
Write Protect (active low)
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock (Bi-directional Mode)
VCLK
Serial Clock (Transmit-Only Mode)
V
CC
+2.5V to 5.5V Power Supply
NC
No Connection
TABLE 1-2:
DC CHARACTERISTICS
V
CC
= +2.5V to 5.5V
Commercial
(C):
Tamb = 0
°
C to +70
°
C
Industrial (I):
Tamb
= -40
°
C to +85
°
C
Parameter
Symbol
Min
Max
Units
Conditions
SCL and SDA pins:
High level input voltage
Low level input voltage
V
IH
V
IL
0.7 V
CC
0.3 V
CC
V
V
Input levels on VCLK pin:
High level input voltage
Low level input voltage
V
IH
V
IL
2.0
0.8
0.2 V
CC
V
V
V
CC
≥
2.7V (Note)
V
CC
< 2.7V (Note)
Hysteresis of Schmitt trigger inputs
V
HYS
.05 V
CC
—
V
(Note)
Low level output voltage
V
OL1
0.4
V
I
OL
= 3 mA, V
CC
= 2.5V (Note 1)
Low level output voltage
V
OL2
0.6
V
I
OL
= 6 mA, V
CC
= 2.5V
Input leakage current
I
LI
-10
10
µ
A
V
IN
= 0.1V to V
CC
Output leakage current
I
LO
-10
10
µ
A
V
OUT
= 0.1V to V
CC
Pin capacitance (all inputs/outputs)
C
INT
10
pF
V
CC
= 5.0V (Note1),
Tamb = 25
°
C, F
CLK
= 1 MHz
Operating current
I
CC
Write
I
CC
Read
—
—
3
1
mA
mA
V
CC
= 5.5V, SCL = 400 kHz
Standby current
I
CCS
—
30
100
µ
A
µ
A
V
CC
= 3.0V, SDA = SCL = V
CC
V
CC
= 5.5V, SDA = SCL = V
CC
Note: This parameter is periodically sampled and not 100% tested.
©
1996 Microchip Technology Inc.
DS21127B-page 3
24LCS21
TABLE 1-3:
AC CHARACTERISTICS
Parameter
Symbol
Vcc= 2.5-5.5V
Vcc= 4.5 - 5.5V
Units
Remarks
Min
Max
Min
Max
Clock frequency
F
CLK
0
100
0
400
kHz
Clock high time
T
HIGH
4000
—
600
—
ns
Clock low time
T
LOW
4700
—
1300
—
ns
SDA and SCL rise time
T
R
—
1000
—
300
ns
(Note 1)
SDA and SCL fall time
T
F
—
300
—
300
ns
(Note 1)
START condition hold time
T
HD
:
STA
4000
—
600
—
ns
After this period the first clock
pulse is generated
START condition setup time
T
SU
:
STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—
0
—
ns
(Note 2)
Data input setup time
T
SU
:
DAT
250
—
100
—
ns
STOP condition setup time
T
SU
:
STO
4000
—
600
—
ns
Output valid from clock
T
AA
—
3500
—
900
ns
(Note 2)
Bus free time
T
BUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission can
start
Output fall time from V
IH
minimum to V
IL
maximum
T
OF
—
250
20 + 0.1
C
B
250
ns
(Note 1), C
B
≤
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
—
100
—
50
ns
(Note 3)
Write cycle time
T
WR
—
10
—
10
ms
Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK
T
VAA
—
2000
—
1000
ns
VCLK high time
T
VHIGH
4000
—
600
—
ns
VCLK low time
T
VLOW
4700
—
1300
—
ns
VCLK setup time
T
VHST
0
—
0
—
ns
VCLK hold time
T
SPVL
4000
—
600
—
ns
Mode transition time
T
VHZ
—
500
—
500
ns
Transmit-Only power up time
T
VPU
0
—
0
—
ns
Input filter spike suppression
(VCLK pin)
T
SPV
—
100
—
100
ns
Endurance
—
10M
—
10M
—
cycles
25
°
C, V
CC
= 5.0V, Block Mode
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to Schmitt trigger inputs which provide noise and spike
suppression. This eliminates the need for a T
I
specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
24LCS21
DS21127B-page 4
©
1996 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24LCS21 operates in two modes, the
Transmit-Only Mode and the bi-directional Mode. There
is a separate two wire protocol to support each mode,
each having a separate clock input but sharing a com-
mon data line (SDA). The device enters the Trans-
mit-Only Mode upon power-up. In this mode, the device
transmits data bits on the SDA pin in response to a
clock signal on the VCLK pin. The device will remain in
this mode until a valid high to low transition is placed on
the SCL input. When a valid transition on SCL is recog-
nized, the device will switch into the bi-directional
Mode. The only way to switch the device back to the
Transmit-Only Mode is to remove power from the
device.
2.1
Transmit-Only Mode
The device will power up in the Transmit-Only Mode at
address 00H. This mode supports a unidirectional two
wire protocol for continuous transmission of the
contents of the memory array. This device requires that
it be initialized prior to valid data being sent in the Trans-
mit-Only Mode (see Initialization Procedure, below). In
this mode, data is transmitted on the SDA pin in 8-bit
bytes, with each byte followed by a ninth, null bit
Mode is provided on the VCLK pin, and a data bit is out-
put on the rising edge on this pin. The eight bits in each
byte are transmitted most significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the internal address pointers will wrap around to the
first memory location (00H) and continue. The bi-direc-
tional Mode Clock (SCL) pin must be held high for the
device to remain in the Transmit-Only Mode.
2.2
Initialization Procedure
After V
CC
has stabilized, the device will be in the
Transmit-Only Mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit in address
FIGURE 2-1: TRANSMIT ONLY MODE
FIGURE 2-2: DEVICE INITIALIZATION
SCL
SDA
VCLK
T
VAA
T
VAA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB)
Bit 7
T
VLOW
T
VHIGH
T
VAA
T
VAA
Bit 8
Bit 7
High Impedance for 9 clock cycles
T
VPU
1
2
8
9
10
11
SCL
SDA
VCLK
Vcc
©
1996 Microchip Technology Inc.
DS21127B-page 5
24LCS21
3.0
BI-DIRECTIONAL MODE
The 24LCS21 can be switched into the bi-directional
transition on the bi-directional Mode Clock (SCL).
When the device has been switched into the bi-direc-
tional Mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two-wire bi-direc-
tional data transmission protocol (I
2
C
™
). In this proto-
col, a device that sends data on the bus is defined to be
the transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be con-
trolled by a master device that generates the bi-direc-
tional Mode Clock (SCL), controls access to the bus
and generates the START and STOP conditions, while
the 24LCS21 acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
In this mode, the 24LCS21 only responds to commands
for device 1010 000X.
3.1 Bi-directional Mode Bus Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
3.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
3.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
FIGURE 3-1: MODE TRANSITION
FIGURE 3-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
VCLK
Bi-directional Mode
T
VHZ
Transmit Only Mode
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
SDA
24LCS21
DS21127B-page 6
©
1996 Microchip Technology Inc.
3.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
Note:
Once switched into bi-directional Mode,
the 24LCS21 will remain in that mode until
power goes away. Removing power is the
only way to reset the 24LCS21 into the
Transmit-only mode.
3.1.5
ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Note:
The 24LCS21 does not generate any
acknowledge bits if an internal
programming cycle is in progress.
FIGURE 3-3: BUS TIMING START/STOP
FIGURE 3-4: BUS TIMING DATA
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
©
1996 Microchip Technology Inc.
DS21127B-page 7
24LCS21
3.1.6
SLAVE ADDRESS
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010000) for the 24LCS21.
The eighth bit of slave address determines whether the
master device wants to read or write to the 24LCS21
The 24LCS21 monitors the bus for its corresponding
slave address continuously. It generates an
acknowledge bit if the slave address was true and it is
not in a programming mode.
FIGURE 3-5: CONTROL BYTE ALLOCATION
Operation
Slave Address
R/W
Read
1010000
1
Write
1010000
0
SLAVE ADDRESS
1
0
1
0
0
0
0
R/W
A
START
READ/WRITE
4.0
WRITE OPERATION
4.1
Byte Write
Following the start signal from the master, the slave
address (4 bits), three zero bits (000) and the R/W bit
which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LCS21. After receiving
another acknowledge signal from the 24LCS21 the
master device will transmit the data word to be written
into the addressed memory location. The 24LCS21
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24LCS21 will not generate acknowl-
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high to low during the self-timed
program operation will not halt programming of the
device.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: VCLK WRITE ENABLE TIMING
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY: