©
1996 Microchip Technology Inc.
DS21124C-page 1
FEATURES
• Voltage operating range: 1.8V to 6.0V
- Peak write current 3 mA at 6.0V
- Maximum read current 150
µ
A at 6.0V
- Standby current 1
µ
A typical
• Industry standard two-wire bus protocol, I
2
C
™
compatible
- Including 100 kHz (1.8V) and 400 kHz (5V)
modes
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Endurance:
- 10,000,000 Erase/Write (E/W) cycles guaran-
teed for High Endurance Block
- 1,000,000 E/W cycles guaranteed for Stan-
dard Endurance Block
• 8 byte page, or byte modes available
• 1 page x 8 line input cache (64 bytes) for fast write
loads
• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Factory programming (QTP) available
• Up to 8 devices may be connected to the same
bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24AA32 is a 4K x 8 (32K
bit) Serial Electrically Erasable PROM capable of oper-
ation across a broad voltage range (1.8V to 6.0V). This
device has been developed for advanced, low power
applications such as personal communications or data
acquisition. The 24AA32 features an input cache for
fast write loads with a capacity of eight 8-byte pages, or
64 bytes. It also features a fixed 4K-bit block of ultra-
high endurance memory for data that changes fre-
quently. The 24AA32 is capable of both random and
sequential reads up to the 32K boundary. Functional
address lines allow up to 8 - 24AA32 devices on the
same bus, for up to 256K bits address space. Advanced
CMOS technology and broad voltage range make this
device ideal for low-power/low voltage, nonvolatile code
- Commercial (C):
0
°
C to +70
°
C
PACKAGE TYPES
BLOCK DIAGRAM
and data applications. The 24AA32 is available in the
standard 8-pin plastic DIP and 8-pin surface mount
SOIC package.
24AA32
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
NC
SCL
SDA
24AA32
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
V
CC
NC
SCL
SDA
PDIP
SOIC
HV GENERATOR
EEPROM ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
I/O
SCL
V
CC
V
SS
A0..A2
SDA
Cache
24AA32
32K 1.8V I
2
C
™
Smart Serial EEPROM
I
2
C is a trademark of Philips Corporation.
This document was created with FrameMaker 4 0 4
24AA32
DS21124C-page 2
©
1996 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
V
CC
..................................................................................7.0V
All inputs and outputs w.r.t. V
SS
............... -0.6V to V
CC
+1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied ................ -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins
..................................................≥
4 kV
*Notice:
Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
PIN FUNCTION TABLE
Name
Function
A0..A2
User Configurable Chip Selects
V
SS
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
V
CC
+1.8V to 6.0V Power Supply
NC
No Internal Connection
TABLE 1-2:
DC CHARACTERISTICS
FIGURE 1-1:
BUS TIMING START/STOP
V
CC
= +1.8V to 6.0V
Commercial (C):
Tamb
= 0˚C to +70˚C
Industrial (I):
Tamb
= -40˚C to +85˚C
Parameter
Symbol
Min
Max
Units
Conditions
A0, A1, A2, SCL and SDA pins:
High level input voltage
V
IH
.7 V
CC
—
V
Low level input voltage
V
IL
—
.3 Vcc
V
Hysteresis of Schmitt Trigger inputs
V
HYS
.05 V
CC
—
V
(Note)
Low level output voltage
V
OL
—
.40
V
I
OL
= 3.0 mA
Input leakage current
I
LI
-10
10
µ
A
V
IN
= .1V to V
CC
Output leakage current
I
LO
-10
10
µ
A
V
OUT
= .1V to V
CC
Pin capacitance
(all inputs/outputs)
C
IN
,
C
OUT
—
10
pF
V
CC
= 5.0V Note 1
Tamb = 25˚C, Fclk = 1 MHz
Operating current
I
CC
Write
I
CC
Read
—
—
3
150
mA
µ
A
V
CC
= 6.0V, SCL = 400 kHz
V
CC
= 6.0V, SCL = 400 kHz
Standby current
I
CCS
—
5
2
µ
A
µ
A
V
CC
= 5.0V, SCL = SDA = V
CC
(Note)
V
CC
= 1.8V, SCL = SDA = V
CC
(Note)
Note:
This parameter is periodically sampled and not 100% tested.
T
SU
:
STA
T
HD
:
STA
V
HYS
T
SU
:
STO
START
STOP
SCL
SDA
©
1996 Microchip Technology Inc.
DS21124C-page 3
24AA32
TABLE 1-3:
AC CHARACTERISTICS
FIGURE 1-2:
BUS TIMING DATA
Parameter
Symbol
V
CC
= 1.8V-6.0V
STD. MODE
V
CC
= 4.5 - 6.0V
FAST MODE
Units
Remarks
Min
Max
Min
Max
Clock frequency
F
CLK
—
100
—
400
kHz
Clock high time
T
HIGH
4000
—
600
—
ns
Clock low time
T
LOW
4700
—
1300
—
ns
SDA and SCL rise time
T
R
—
1000
—
300
ns
(Note 1)
SDA and SCL fall time
T
F
—
300
—
300
ns
(Note1)
START condition hold time
T
HD
:
STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
START condition setup time
T
SU
:
STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
T
HD
:
DAT
0
—
0
—
ns
Data input setup time
T
SU
:
DAT
250
—
100
—
ns
STOP condition setup time
T
SU
:
STO
4000
—
600
—
ns
Output valid from clock
T
AA
—
3500
—
900
ns
(Note 2)
Bus free time
T
BUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission
can start
Output fall time from V
IH
min to
V
IL
max
T
OF
—
250
20 +0.1
C
B
250
ns
(Note 1), C
B
≤
100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP
—
50
—
50
ns
(Note 3)
Write cycle time
T
WR
—
5
—
5
ms/page (Note 4)
Endurance
High Endurance Block
Rest of Array
—
—
10M
1M
—
—
10M
1M
—
—
cycles
25
°
C, Vcc = 5.0V, Block
Note 1: Not 100% tested. C
B
= total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
4: The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
5: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
SCL
SDA
IN
SDA
OUT
T
SU
:
STA
T
SP
T
AA
T
F
T
LOW
T
HIGH
T
HD
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
T
AA
T
R
24AA32
DS21124C-page 4
©
1996 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24AA32 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24AA32 works
as slave. Both master and slave can operate as trans-
mitter or receiver but the master device determines
which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave (24AA32) will leave the data line HIGH
to enable the master to generate the STOP condition.
Note:
The 24AA32 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(A)
(C)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
SCL
SDA
©
1996 Microchip Technology Inc.
DS21124C-page 5
24AA32
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code; for the 24AA32 this
is set as 1010 binary for read and write operations. The
next three bits of the control byte are the device select
bits (A2, A1, A0). They are used by the master device
to select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte defines
the operation to be performed. When set to a one a
read operation is selected, and when set to a zero a
write operation is selected. The next two bytes received
define the address of the first data byte (Figure 3-3).
Because only A11...A0 are used, the upper four
address bits must be zeros. The most significant bit of
the most significant byte of the address is transferred
first.
Following the start condition, the 24AA32 monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving a 1010 code and appropri-
ate device select bits, the slave device outputs an
acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the 24AA32 will select a read or
write operation.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
Operation
Control
Code
Device Select
R/W
Read
1010
Device Address
1
Write
1010
Device Address
0
SLAVE ADDRESS
1
0
1
0
A2
A1
A0
R/W
A
START
READ/WRITE
FIGURE 3-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
0
1
0
A
2
A
1
A
0 R/W
0
0
0
0
A
11
A
10
A
9
A
7
A
0
A
8
•
•
•
•
•
•
SLAVE
ADDRESS
DEVICE
SELECT
BUS
CONTROL BYTE
ADDRESS BYTE 1
ADDRESS BYTE 0
This document was created with FrameMaker 4 0 4
24AA32
DS21124C-page 6
©
1996 Microchip Technology Inc.
4.0
WRITE OPERATION
4.1
Split Endurance
The 24AA32 is organized as a continuous 32K block of
memory. However, the first 4K, starting at address 000,
is rated at 10,000,000 E/W cycles guaranteed. The
remainder of the array, 28K bits, is rated at 100,000 E/
W cycles guaranteed. This feature is helpful in applica-
tions in which some data change frequently, while a
majority of the data change infrequently. One example
would be a cellular telephone in which last-number
redial and microcontroller scratch pad require a high-
endurance block, while speed dials and lookup tables
change infrequently and so require only a standard
endurance rating.
4.2
Byte Write
Following the start condition from the master, the con-
trol code (four bits), the device select (three bits), and
the R/W bit which is a logic low are clocked onto the bus
by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will follow after it has generated an acknowl-
edge bit during the ninth clock cycle. Therefore the next
byte transmitted by the master is the high-order byte of
the word address and will be written into the address
pointer of the 24AA32. The next byte is the least signif-
icant address byte. After receiving another acknowl-
edge signal from the 24AA32 the master device will
transmit the data word to be written into the addressed
memory location.
The 24AA32 acknowledges again and the master gen-
erates a stop condition. This initiates the internal write
cycle, and during this time the 24AA32 will not generate
4.3
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24AA32 in the same way as
in a byte write. But instead of generating a stop condi-
tion, the master transmits up to eight pages of eight
data bytes each (64 bytes total) which are temporarily
stored in the on-chip page cache of the 24AA32. They
will be written from cache into the EEPROM array after
the master has transmitted a stop condition. After the
receipt of each word, the six lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remain con-
stant. If the master should transmit more than eight
bytes prior to generating the stop condition (writing
across a page boundary), the address counter (lower
three bits) will roll over and the pointer will be incre-
mented to point to the next line in the cache. This can
continue to occur up to eight times or until the cache is
full, at which time a stop condition should be generated
by the master. If a stop condition is not received, the
cache pointer will roll over to the first line (byte 0) of the
cache, and any further data received will overwrite pre-
viously captured data. The stop condition can be sent
at any time during the transfer. As with the byte write
operation, once a stop condition is received, an internal
write cycle will begin. The 64-byte cache will continue
to capture data until a stop condition occurs or the oper-
FIGURE 4-1:
BYTE WRITE
FIGURE 4-2:
S
t
a
r
t
Control
Byte
Word
Address (1)
Word
Address (0)
Data
S
t
o
p
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity:
Master
SDA Line
Bus Activity
0 0 0 0
S
t
a
r
t
Control
Byte
Word
Address (1)
Word
Address (0)
A
C
K
A
C
K
A
C
K
A
C
K
Bus Activity:
Master
SDA Line
Bus Activity
S
t
o
p
A
C
K
Data n
Data n + 15
0 0 0 0
7
©
1996 Microchip Technology Inc.
DS21124C-page 7
24AA32
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
FIGURE 5-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
6.0
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
6.1
Current Address Read
The 24AA32 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n (n is
any legal address), the next current address read oper-
ation would access data from address n + 1. Upon
receipt of the slave address with R/W bit set to one, the
24AA32 issues an acknowledge and transmits the eight
bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the