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1996 Microchip Technology Inc.

DS20071H-page 1

FEATURES

• Single supply with operation down to 2.5V

• Low power CMOS technology

- 1 mA active current typical

- 10

A standby current typical at 5.5V

- 5

A standby current typical at 3.0V

• Organized as a single block of 128 bytes (128 x 8)

or 256 bytes (256 x 8)

• 2-wire serial interface bus, I

™

compatible

• 100kHz (2.5V) and 400kHz (5.0V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• ESD protection > 3,000V

• 10,000,000 ERASE/WRITE cycles guaranteed on

24LC01B

• 1,000,000 E/W cycles guaranteed on 24LC02B

• Data retention > 200 years

• 8 pin DIP or SOIC package

• Available for extended temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24LC01B and 24LC02B

are 1K bit and 2K bit Electrically Erasable PROMs. The

devices are organized as a single block of 128 x 8 bit or

256 x 8 bit memory with a two wire serial interface. Low

voltage design permits operation down to 2.5 volts with

a standby and active currents of only 5

A and 1 mA

respectively. The 24LC01B and 24LC02B also have

page-write capability for up to 8 bytes of data. The

24LC01B and 24LC02B are available in the standard

8-pin DIP and an 8-pin surface mount SOIC package.

- Commercial (C):

0˚C to

+70˚C

- Industrial (I):

-40˚C to

+85˚C

PACKAGE TYPES

BLOCK DIAGRAM

24LC01B/02B

Vss

Vcc

SCL

SDA

Vss

Vcc

SCL

SDA

PDIP

SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA SCL

24LC01B/02B

1K/2K 2.5V I

™

Serial EEPROM

C is a trademark of Philips Corporation.

This document was created with FrameMaker 4 0 4

24LC01B/02B

DS20071H-page 2

1996 Microchip Technology Inc.

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

...................................................................................7.0V

All inputs and outputs w.r.t. V

............... -0.6V to V

+1.0V

Storage temperature ..................................... -65˚C to +150˚C

Ambient temp. with power applied ................ -65˚C to +125˚C

Soldering temperature of leads (10 seconds) ............. +300˚C

ESD protection on all pins.............................................

≥

4 kV

*Notice:

Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

PIN FUNCTION TABLE

Name

Function

SDA

SCL

A0, A1, A2

Ground

Serial Address/Data I/O

Serial Clock

Write Protect Input

+2.5V to 5.5V Power Supply

No Internal Connection

TABLE 1-2:

DC CHARACTERISTICS

FIGURE 1-1:

BUS TIMING START/STOP

= +2.5V to +5.5V

Commercial (C): Tamb = 0˚C to +70˚C

Industrial

(I): Tamb = -40˚C to +85˚C

Parameter

Symbol

Min.

Max.

Units

Conditions

WP, SCL and SDA pins:

High level input voltage

.7 V

Low level input voltage

.3 V

Hysteresis of Schmidt trigger inputs

HYS

.05 V

—

(Note)

Low level output voltage

.40

= 3.0 mA, V

= 2.5V

Input leakage current

-10

= .1V to 5.5V

Output leakage current

-10

OUT

= .1V to 5.5V

Pin capacitance (all inputs/outputs)

OUT

—

= 5.0V (Note 1)

Tamb = 25˚C, F

CLK

= 1 MHz

Operating current

Write

—

= 5.5V, SCL = 400 kHz

Read

—

Standby current

CCS

—

= 3.0V, SDA = SCL = V

100

= 5.5V, SDA = SCL = V

Note:

This parameter is periodically sampled and not 100% tested.

SCL

SDA

STA

START

STOP

HYS

STO

1996 Microchip Technology Inc.

DS20071H-page 3

24LC01B/02B

TABLE 1-3:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

STANDARD

MODE

Vcc = 4.5 - 5.5V

FAST MODE

Units

Remarks

Min.

Max.

Min.

Max.

Clock frequency

CLK

—

100

—

400

kHz

Clock high time

HIGH

4000

—

600

—

Clock low time

LOW

4700

—

1300

—

SDA and SCL rise time

—

1000

—

300

(Note 1)

SDA and SCL fall time

—

300

—

300

(Note 1)

START condition hold time

STA

4000

—

600

—

After this period the ﬁrst

clock pulse is generated

START condition setup time

STA

4700

—

600

—

Only relevant for repeated

START condition

Data input hold time

DAT

—

(Note 2)

Data input setup time

DAT

250

—

100

—

STOP condition setup time

STO

4000

—

600

—

Output valid from clock

—

3500

—

900

(Note 2)

Bus free time

BUF

4700

—

1300

—

Time the bus must be free

before a new transmission

can start

Output fall time from V

minimum to V

maximum

—

250

20 +0.1

250

(Note 1), CB

≤

100 pF

Input ﬁlter spike suppression

(SDA and SCL pins)

—

(Note 3)

Write cycle time

—

Byte or Page mode

Endurance

24LC01B

—

10M

—

10M

—

cycles

C, Vcc = 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

and V

HYS

speciﬁcations are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI speciﬁcation for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

SCL

SDA

OUT

STA

HIGH

STO

DAT

BUF

STA

LOW

24LC01B/02B

DS20071H-page 4

1996 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

The 24LC01B/02B supports a bi-directional two wire

bus and data transmission protocol. A device that

sends data onto the bus is deﬁned as transmitter, and

a device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions, while the

24LC01B/02B works as slave. Both master and slave

can operate as transmitter or receiver but the master

device determines which mode is activated.

3.0

BUS CHARACTERISTICS

The following

bus protocol

has been deﬁned:

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last six-

teen will be stored when doing a write operation. When

an overwrite does occur it will replace data in a ﬁrst in

ﬁrst out fashion.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

Note:

The 24LC01B/02B does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

FIGURE 3-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(

)

(B)

(D)

(C)

(

)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

1996 Microchip Technology Inc.

DS20071H-page 5

24LC01B/02B

3.6

Devide Address

The 24LC01B/02B are software-compatible with older

devices such as 24C01A, 24C02A, 24LC01, and

24LC02. A single 24LC02B can be used in place of two

24LC01's, for example, without any modiﬁcations to

software. The “chip select” portion of the control byte

becomes a don't care.

After generating a START condition, the bus master

transmits the slave address consisting of a 4-bit device

code (1010) for the 24LC01B/02B, followed by three

don't care bits.

The eighth bit of slave address determines if the master

device wants to read or write to the 24LC01B/02B

(Figure 3-2).

The 24LC01B/02B monitors the bus for its correspond-

ing slave address all the time. It generates an acknowl-

edge bit if the slave address was true and it is not in a

programming mode.

FIGURE 3-2:

CONTROL BYTE

ALLOCATION

Operation

Control

Code

Chip

Select

R/W

Read

Write

1010

XXX

X = Don’t care

R/W

READ/WRITE

START

SLAVE ADDRESS

4.0

WRITE OPERATION

4.1

Byte Write

Following the start signal from the master, the device

code (4 bits), the don't care bits (3 bits), and the R/W bit

which is a logic low is placed onto the bus by the master

transmitter. This indicates to the addressed slave

receiver that a byte with a word address will follow after

it has generated an acknowledge bit during the ninth

clock cycle. Therefore the next byte transmitted by the

master is the word address and will be written into the

address pointer of the 24LC01B/02B. After receiving

another acknowledge signal from the 24LC01B/02B the

master device will transmit the data word to be written

into the addressed memory location. The 24LC01B/

02B acknowledges again and the master generates a

stop condition. This initiates the internal write cycle,

and during this time the 24LC01B/02B will not generate

acknowledge signals (Figure 4-1).

4.2

Page Write

The write control byte, word address and the ﬁrst data

byte are transmitted to the 24LC01B/02B in the same

way as in a byte write. But instead of generating a stop

condition the master transmits up to eight data bytes to

the 24LC01B/02B which are temporarily stored in the

on-chip page buffer and will be written into the memory

after the master has transmitted a stop condition. After

the receipt of each word, the three lower order address

pointer bits are internally incremented by one. The

higher order ﬁve bits of the word address remains con-

stant. If the master should transmit more than eight

words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 4-2).

FIGURE 4-1:

BYTE WRITE

FIGURE 4-2:

PAGE WRITE

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS

DATA

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATAn + 7

DATAn + 1

24LC01B/02B

DS20071H-page 6

1996 Microchip Technology Inc.

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for ﬂow diagram.

FIGURE 5-1:

ACKNOWLEDGE POLLING

FLOW

6.0

WRITE PROTECTION

The 24LC01B/02B can be used as a serial ROM when

the WP pin is connected to V

. Programming will be

inhibited and the entire memory will be write-protected.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

7.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

7.1

Current Address Read

The 24LC01B/02B contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by one. Therefore, if the previous

access (either a read or write operation) was to address

n, the next current address read operation would

access data from address n + 1. Upon receipt of the

slave address with R/W bit set to one, the 24LC01B/

02B issues an acknowledge and transmits the eight bit

data word. The master will not acknowledge the transfer

but does generate a stop condition and the 24LC01B/

02B discontinues transmission (Figure 7-1).

7.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, ﬁrst the word address must

be set. This is done by sending the word address to the

24LC01B/02B as part of a write operation. After the

word address is sent, the master generates a start con-

dition following the acknowledge. This terminates the

write operation, but not before the internal address

pointer is set. Then the master issues the control byte

again but with the R/W bit set to a one. The 24LC01B/

02B will then issue an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the transfer but does generate a stop condition and the

24LC01B/02B discontinues transmission (Figure 7-2).

7.3

Sequential Read

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24LC01B/02B transmits

the ﬁrst data byte, the master issues an acknowledge

as opposed to a stop condition in a random read. This

directs the 24LC01B/02B to transmit the next sequen-

tially addressed 8-bit word (Figure 7-3).

To provide sequential reads the 24LC01B/02B contains

an internal address pointer which is incremented by

one at the completion of each operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

7.4

Noise Protection

The 24LC01B/02B employs a V

threshold detector

circuit which disables the internal erase/write logic if the

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.