55X.bk

1997 Microchip Technology Inc.

Preliminary

DS40143B-page 1

Devices included in this data sheet:

Referred to collectively as PIC16C55X(A).

• PIC16C554

PIC16C554A

PIC16C556A

• PIC16C558

PIC16C558A

High Performance RISC CPU:

• Only 35 instructions to learn

• All single-cycle instructions (200 ns), except for

program branches which are two-cycle

• Operating speed:

- DC - 20 MHz clock input

- DC - 200 ns instruction cycle

• Interrupt capability

• 16 special function hardware registers

• 8-level deep hardware stack

• Direct, Indirect and Relative addressing modes

Peripheral Features:

• 13 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

Special Microcontroller Features:

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

Device

Program

Memory

Data

Memory

PIC16C554

512

PIC16C554A

512

PIC16C556A

PIC16C558

128

PIC16C558A

128

Pin Diagram

Special Microcontroller Features (cont’d)

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Serial in-circuit programming (via two pins)

• Four user programmable ID locations

CMOS Technology:

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range

- 2.5V to 5.5V PIC16C55X

- 3.0 to 5.5V PIC16C55XA

• Commercial, industrial and extended tempera-

ture range

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

- 15

A typical @ 3.0V, 32 kHz

- < 1.0

A typical standby current @ 3.0V

RA1

RA0

OSC2/CLKOUT

RB7

RB6

RB5

RB4

OSC1/CLKIN

RA2

RA3

MCLR

RB0/INT

RB1

RB2

RB3

RA4/T0CKI

RA1

RA0

OSC2/CLKOUT

RB7

RB6

RB5

RB4

OSC1/CLKIN

RA2

RA3

MCLR

RB0/INT

RB1

RB2

RA4/T0CKI

PIC16C55X(A)

RB3

PDIP, SOIC, Windowed CERDIP

SSOP

•1

PIC16C55X(A)

EPROM-Based 8-Bit CMOS Microcontroller

PIC16C55X(A)

1997 Microchip Technology Inc.

Preliminary

DS40143B-page 5

PIC16C55X(A)

1.0

GENERAL DESCRIPTION

The PIC16C55X(A) are 18 and 20-Pin EPROM-based

members of the versatile PIC16CXX family of low-cost,

high-performance, CMOS, fully-static, 8-bit

microcontrollers.

All

PICmicro™ microcontrollers employ an advanced

RISC architecture. The PIC16C55X(A) have enhanced

core features, eight-level deep stack, and multiple inter-

nal and external interrupt sources. The separate

instruction and data buses of the Harvard architecture

allow a 14-bit wide instruction word with the separate

8-bit wide data. The two-stage instruction pipeline

allows all instructions to execute in a single-cycle,

except for program branches (which require two

cycles). A total of 35 instructions (reduced instruction

set) are available. Additionally, a large register set gives

some of the architectural innovations used to achieve a

very high performance.

PIC16C55X(A) microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

The PIC16C554(A) and PIC16C556A have 80 bytes of

RAM. The PIC16C558(A) has 128 bytes of RAM. Each

device has 13 I/O pins and an 8-bit timer/counter with

an 8-bit programmable prescaler.

PIC16C55X(A) devices have special features to reduce

external components, thus reducing cost, enhancing

system reliability and reducing power consumption.

There are four oscillator options, of which the single pin

RC oscillator provides a low-cost solution, the LP

oscillator minimizes power consumption, XT is a

standard crystal, and the HS is for High Speed crystals.

The SLEEP (power-down) mode offers power saving.

The user can wake up the chip from SLEEP through

several external and internal interrupts and reset.

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against software

lock- up.

A UV-erasable CERDIP-packaged version is ideal for

code development while the cost-effective One-Time

Programmable (OTP) version is suitable for production

in any volume.

Table 1-1 shows the features of the PIC16C55X(A)

mid-range microcontroller families.

A simpliﬁed block diagram of the PIC16C55X(A) is

shown in Figure 3-1.

The PIC16C55X(A) series ﬁt perfectly in applications

ranging from motor control to low-power remote sen-

sors. The EPROM technology makes customization of

application programs (detection levels, pulse genera-

tion, timers, etc.) extremely fast and convenient. The

small footprint packages make this microcontroller

series perfect for all applications with space limitations.

Low-cost, low-power, high-performance, ease of use

and I/O ﬂexibility make the PIC16C55X(A) very versa-

tile.

1.1

Family and Upward Compatibility

Those users familiar with the PIC16C5X family of

microcontrollers will realize that this is an enhanced

version of the PIC16C5X architecture. Please refer to

Appendix A for a detailed list of enhancements. Code

written for PIC16C5X can be easily ported to

PIC16C55X(A) family of devices (Appendix B).

The PIC16C55X(A) family ﬁlls the niche for users want-

ing to migrate up from the PIC16C5X family and not

needing various peripheral features of other members

of the PIC16XX mid-range microcontroller family.

1.2

Development Support

The PIC16C55X(A) family is supported by a full-fea-

tured macro assembler, a software simulator, an in-cir-

cuit emulator, a low-cost development programmer and

a full-featured programmer. A “C” compiler and fuzzy

logic support tools are also available.

PIC16C55X(A)

DS40143B-page 6

Preliminary

1997 Microchip Technology Inc.

TABLE 1-1:

PIC16C55X(A) FAMILY OF DEVICES

PIC16C554

PIC16C554A

PIC16C556A

PIC16C558

PIC16C558A

Clock

Maximum Frequency of Oper-

ation (MHz)

Memory

EPROM Program Memory

(x14 words)

512

Data Memory (bytes)

128

Peripherals

Timer Module(s)

TMR0

Features

Interrupt Sources

I/O Pins

Voltage Range (Volts)

2.5-5.5

3.0-5.5

2.5-5.5

3.0-5.5

Brown-out Reset

—

Packages

18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

18-pin DIP,

SOIC;

20-pin SSOP

All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high

I/O current capability. All PIC16C55X(A)Family devices use serial programming with clock pin RB6 and data pin RB7.

1997 Microchip Technology Inc.

Preliminary

DS40143B-page 7

PIC16C55X(A)

2.0

PIC16C55X(A) DEVICE

VARIETIES

A variety of frequency ranges and packaging options are

available. Depending on application and production

requirements the proper device option can be selected

using the information in the PIC16C55X(A) Product

Identiﬁcation System section at the end of this data

sheet. When placing orders, please use this page of the

data sheet to specify the correct part number.

2.1

UV Erasable Devices

The UV erasable version, offered in CERDIP package

is optimal for prototype development and pilot

programs. This version can be erased and

reprogrammed to any of the oscillator modes.

Microchip's PICSTART

and PROMATE

programmers both support programming of the

PIC16C55X(A).

2.2

One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the ﬂexibility for frequent code

updates and small volume applications. In addition to

the program memory, the conﬁguration bits must also

be programmed.

2.3

Quick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code pat-

terns have stabilized. The devices are identical to the

OTP devices but with all EPROM locations and conﬁg-

uration options already programmed by the factory.

Certain code and prototype veriﬁcation procedures

apply before production shipments are available.

Please contact your Microchip Technology sales ofﬁce

for more details.

2.4

Serialized

Quick-Turnaround-Production

(SQTP

) Devices

Microchip offers a unique programming service where

a few user-deﬁned locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

1997 Microchip Technology Inc.

Preliminary

DS40143B-page 9

PIC16C55X(A)

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16C55X(A) family can

be attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16C55X(A) uses a Harvard architecture,

in which, program and data are accessed from sepa-

rate memories using separate busses. This improves

bandwidth over traditional von Neumann architecture

where program and data are fetched from the same

memory. Separating program and data memory further

allows instructions to be sized differently than 8-bit

wide data words. Instruction opcodes are 14-bits wide

making it possible to have all single word instructions.

A 14-bit wide program memory access bus fetches a

14-bit instruction in a single cycle. A two-stage pipeline

overlaps fetch and execution of instructions.

Consequently, all instructions (35) execute in a sin-

gle-cycle (200 ns @ 20 MHz) except for program

branches.

The PIC16C554(A) addresses 512 x 14 on-chip pro-

gram memory. The PIC16C556A addresses 1K x 14

program memory. The PIC16C558(A) addresses 2K x

14 program memory. All program memory is internal.

The PIC16C55X(A) can directly or indirectly address its

registers including the program counter are mapped

into the data memory. The PIC16C55X(A) have an

orthogonal (symmetrical) instruction set that makes it

possible to carry out any operation on any register

using any addressing mode. This symmetrical nature

and lack of ‘special optimal situations’ make program-

ming with the PIC16C55X(A) simple yet efﬁcient. In

addition, the learning curve is reduced signiﬁcantly.

The PIC16C55X(A) devices contain an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the working register

The other operand is a ﬁle register or an

immediate constant. In single operand instructions, the

operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a Borrow and Digit Borrow out bit,

respectively, in subtraction. See the

SUBLW

and

SUBWF

instructions for examples.

A simpliﬁed block diagram is shown in Figure 3-1, with

a description of the device pins in Table 3-1.

PIC16C55X(A)

DS40143B-page 10

Preliminary

1997 Microchip Technology Inc.

FIGURE 3-1:

BLOCK DIAGRAM

Note 1: Higher order bits are from the status register.

Device

Program

Memory

Data Memory

(RAM)

PIC16C554

PIC16C554A

PIC16C556A

PIC16C558

PIC16C558A

512 x 14

1K x 14

2K x 14

80 x 8

128 x 8

EPROM

Program

Memory

2K x 14

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

128 x 8

Direct Addr

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

, V

Timer0

PORTA

PORTB

RA1

RA4/T0CKI

RB0/INT

RB7:RB1

RAM Addr

(1)

RA0

RA2

RA3

512 x 14

80 x 8 to

1997 Microchip Technology Inc.

Preliminary

DS40143B-page 11

PIC16C55X(A)

TABLE 3-1:

PIC16C55X(A) PINOUT DESCRIPTION

Name

DIP

SOIC

Pin #

SSOP

Pin #

I/O/P

Type

Buffer

Type

Description

OSC1/CLKIN

ST/CMOS Oscillator crystal input/external clock source input.

OSC2/CLKOUT

—

Oscillator crystal output. Connects to crystal or resonator

in crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

MCLR/V

I/P

Master clear (reset) input/programming voltage input.

This pin is an active low reset to the device.

PORTA is a bi-directional I/O port.

RA0

I/O

RA1

I/O

RA2

I/O

RA3

I/O

RA4/T0CKI

I/O

Can be selected to be the clock input to the Timer0

timer/counter. Output is open drain type.

PORTB is a bi-directional I/O port. PORTB can be

software programmed for internal weak pull-up on all

inputs.

RB0/INT

I/O

TTL/ST

(1)

RB0/INT can also be selected as an external

interrupt pin.

RB1

I/O

TTL

RB2

I/O

TTL

RB3

I/O

TTL

RB4

I/O

TTL

Interrupt on change pin.

RB5

I/O

TTL

Interrupt on change pin.

RB6

I/O

TTL/ST

(2)

Interrupt on change pin. Serial programming clock.

RB7

I/O

TTL/ST

(2)

Interrupt on change pin. Serial programming data.

5,6

—

Ground reference for logic and I/O pins.

15,16

—

Positive supply for logic and I/O pins.

Legend:

O = output

I/O = input/output

P = power

— = Not used

I = Input

ST = Schmitt Trigger input

TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

PIC16C55X(A)

DS40143B-page 12

Preliminary

1997 Microchip Technology Inc.

3.1

Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The

instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution ﬂow are shown in Figure 3-2.

3.2

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g.,

GOTO

)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2:

CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

OSC1

OSC2/CLKOUT

(RC mode)

PC+1

PC+2

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. CALL SUB_1

Fetch 3

Execute 3

4. BSF PORTA, BIT3

Fetch 4

Flush

Fetch SUB_1 Execute SUB_1

1997 Microchip Technology Inc.

Preliminary

DS40143B-page 13

PIC16C55X(A)

4.0

MEMORY ORGANIZATION

4.1

Program Memory Organization

The PIC16C55X(A) has a 13-bit program counter capa-

ble of addressing an 8K x 14 program memory space.

Only the ﬁrst 512 x 14 (0000h - 01FFh) for the

PIC16C554(A), 1K x 14 (0000h - 03FFh) for the

PIC16C556A and 2K x 14 (0000h - 07FFh) for the

PIC16C558(A) are physically implemented. Accessing

a location above these boundaries will cause a

wrap-around within the ﬁrst 512 x 14 space

PIC16C554(A) or 1K x 14 space PIC16C556A or 2K x

14 space PIC16C558(A). The reset vector is at 0000h

and the interrupt vector is at 0004h (Figure 4-1,

Figure 4-2, Figure 4-3).

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16C554/PIC6C554A

PC<12:0>

000h

0004

0005

01FFh

0200h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

FIGURE 4-2:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16C556A

FIGURE 4-3:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16C558/PIC16C558A

PC<12:0>

000h

0004

0005

03FFh

0400h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program