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MOTOROLA CMOS LOGIC DATA

MC14597B MC14598B

8-Bit Bus-Compatible Latches

The MC14597B and MC14598B are 8–bit latches, one addressed with an

internal counter and the other addressed with an external binary address.

The 8 latch–outputs are high drive, three–state and bus line compatible. The

drive capability allows direct applications with MPU systems such as the

Motorola 6800 family.

With MC14597B, a 3–bit address counter (clocked on the falling edge of

Increment) selects the appropriate latch. The latches of the MC14598B are

accessed via the Address pins, A0, A1, and A2. A Full Flag is provided on

the MC14597B to indicate the position of the Address counter.

All 8 outputs from the latches are available in parallel when Enable is in the

low state. Data is entered into a selected latch from the Data pin when the

Strobe is high. Master reset is available on both parts.

•

Serial Data Input

•

Three–State Bus Compatible Parallel Outputs

•

Three–State Control Pin (Enable) TTL Compatible Input

•

Open Drain Full Flag (Multiple Latch Wire–O Ring)

•

Master Reset

•

Level Shifting Inputs on All Except Enable

•

Diode Protection — All Inputs

•

Supply Voltage Range — 3.0 Vdc to 18 Vdc

•

Capable of Driving TTL Over Rated Temperature Range

With Fanout as Follows:

1 TTL Load

4 LSTTL Loads

BLOCK DIAGRAMS

MC14598B

MC14597B

Enable

Outputs

High Impedance

Dn = State of nth latch

OUTPUT

TRUTH TABLE

VDD

ENABLE

DATA

RESET

VSS

INCREMENT

STROBE

FULL

DATA

RESET

VSS

STROBE

ENABLE

VDD

NC = NO CONNECTION

THREE

STATE

OUTPUT

BUFFERS

LATCHES

ADDRESS

DECODER

3–BIT

ADDRESS

COUNTER

FULL

LOGIC

RESET

LOGIC

RESET

ENABLE

DATA

STROBE

INCREMENT

FULL

VDD = 16

VSS = 8

ENABLE

THREE

STATE

OUTPUT

BUFFERS

LATCHES

ADDRESS

DECODER

VDD = 18

VSS = 9

RESET

DATA

STROBE

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1995

REV 3

1/94

MC14599

See Page 6-174

MC14597B

MC14598B

L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14597BCP

Plastic

MC14597BCL

Ceramic

MC14597BDW

SOIC

TA = – 55

to 125

C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

L SUFFIX

CERAMIC

CASE 726

P SUFFIX

PLASTIC

CASE 707

ORDERING INFORMATION

MC14598BCP

Plastic

MC14598BCL

Ceramic

TA = – 55

to 125

C for all packages.

MOTOROLA CMOS LOGIC DATA

MC14597B MC14598B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

(Voltages Referenced to VSS)

Symbol

Parameter

Value

Unit

VDD

DC Supply Voltage

– 0.5 to + 18.0

Vin

Input Voltage, Enable (DC or Transient)

– 0.5 to VDD + 0.5

Vin

Input Voltage, All other Inputs

(DC or Transient)

– 0.5 to VDD + 12

Vout

Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

Iin, lout

Input or Output Current (DC or Transient),

per Pin

Power Dissipation, per Package†

500

Tstg

Storage Temperature

– 65 to + 150

Lead Temperature (8–Second Soldering)

260

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

“P and D/DW” Packages: – 7.0 mW/C From 65

C To 125

C Ceramic

“L” Packages: – 12 mW/

C From 100

C To 125

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to VSS)

Characteristic

Symbol

VDD

Vdc

– 55

125

Unit

Characteristic

Symbol

VDD

Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

VOL

5.0

—

0.05

—

0.05

—

0.05

Vdc

“1” Level

Vin = 0 or VDD

VOH

5.0

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

—

4.95

9.95

14.95

—

Vdc

Input Voltage** — Enable

“0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

—

0.8

1.6

2.4

—

1.1

2.2

3.4

0.8

1.6

2.4

—

0.8

1.6

2.4

Vdc

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

2.0

6.0

—

2.0

6.0

1.9

3.1

4.3

—

2.0

6.0

—

Vdc

Input Voltage

“0” Level

Other Inputs

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

Vdc

(VO = 0.5 or 4.5 Vdc) “1” Level

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

3.5

7.0

—

3.5

7.0

2.75

5.50

8.25

—

3.5

7.0

—

Vdc

Output Drive Current

Source

(Full — Sink Only)

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

1 5

– 1.0

—

–

—

– 1.0

—

– 2.0

– 6.0

– 12

—

– 1.0

—

mAdc

(VOL = 0.4 Vdc)

Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL

5.0

1.6

—

1.6

—

3.2

6.0

—

1.6

—

mAdc

Input Current

Iin

—

0.1

—

0.00001

0.1

—

1.0

Adc

Three–State Leakage Current

ITL

—

0.1

—

0.00001

0.1

—

3.0

Adc

Input Capacitance (Vin = 0)

Cin

—

5.0

7.5

—

Quiescent Current

(Per Package)

IDD

5.0

—

5.0

—

0.005

0.010

0.015

5.0

—

150

300

600

Adc

**Total Supply Current at an

External Load Capacitance of

130 pF

5.0

IT = (2.0

A/kHz) f + IDD

IT = (4.0

A/kHz) f + IDD

IT = (6.0

A/kHz) f + IDD

Adc

†Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

** The formulas given are for the typical characteristics only at 25

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

operation, Vin and Vout should be constrained

to the range VSS

(Vin or Vout)

VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA

MC14597B MC14598B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS*

(TA = 25

C, CL = 130 pF + 1 TTL Load)

Characteristic

Symbol

VDD

Vdc

All Types

Unit

Characteristic

Symbol

VDD

Vdc

Min

Typ #

Max

Unit

Output Rise and Fall Time

tTLH, tTHL = (0.5 ns/pF) CL + 35 ns

tTLH, tTHL = (0.2 ns/pF) CL + 25 ns

tTLH, tTHL = (0.16 ns/pF) CL + 20 ns

tTLH,

tTHL

5.0

—

100

200

100

Propagation Delay Time

Enable to Output

tPLH,

tPHL

5.0

—

160

125

100

320

250

200

Strobe to Output

5.0

—

200

100

400

200

160

Strobe to Full (MC14597B only)

5.0

—

200

100

400

200

160

Reset to Output

5.0

—

175

350

180

140

Pulse Width

Enable

tWH,

tWL

5.0

320

240

160

120

—

Strobe

5.0

200

100

—

Increment (MC14597B only)

5.0

200

100

—

Reset

5.0

300

160

100

150

—

Setup Time

Data

tsu

5.0

100

—

Address (MC14598B only)

5.0

200

100

—

Increment (MC14597B only)

5.0

400

200

170

200

100

—

Hold Time

Data

5.0

100

—

Address (MC14598B only)

5.0

100

—

Reset Removal Time

trem

5.0

– 25

– 15

– 10

—

* The formulas given are for the typical characteristics only at 25

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA

MC14597B MC14598B

TRUTH TABLE FOR MC14597B

Address

Increment

Enable

Reset

Counter

Full

Count Up

—

No Change

—

Reset to Zero

Set to One

No Change

Set to One

If at

To Zero on

ADDRESS 7

Falling Edge

of STROBE

X = Don’t care

LATCH TRUTH TABLE

Address

Other

Strobe

Reset

Latch

Latches

Data

* = No change in state of latch

X = Don’t care

TEST LOAD

ALL OUTPUTS

+5.0 V

RL = 2.5 k

11.7 k

130 pF

Circuit diagrams external to or containing Motorola prod-

ucts are included as a means of illustration only. Complete

information sufficient for construction purposes may not be

fully illustrated. Although the information herein has been

carefully checked and is believed to be reliable. Motorola

assumes no responsibility for inaccuracies. Information here-

in does not convey to the purchaser any license under the

patent rights of Motorola or others.

The information contained herein is for guidance only, with

no warranty of any type, expressed or implied. Motorola re-

serves the right to make any changes to the information and

the product(s) to which the information applies and to discon-

tinue manufacture of the product(s) at any time.