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MOTOROLA CMOS LOGIC DATA

MC14549B MC14559B

Successive Approximation

Registers

The MC14549B and MC14559B successive approximation registers are

8–bit registers providing all the digital control and storage necessary for

successive approximation analog–to–digital conversion systems. These

parts differ in only one control input. The Master Reset (MR) on the

MC14549B is required in the cascaded mode when more than 8 bits are

desired. The Feed Forward (FF) of the MC14559B is used for register

shortening where End–of–Conversion (EOC) is required after less than eight

cycles.

Applications for the MC14549B and MC14559B include analog–to–digital

conversion, with serial and parallel outputs.

•

Totally Synchronous Operation

•

All Outputs Buffered

•

Single Supply Operation

•

Serial Output

•

Retriggerable

•

Compatible with a Variety of Digital and Analog Systems such as the

MC1408 8–Bit D/A Converter

•

All Control Inputs Positive–Edge Triggered

•

Supply Voltage Range = 3.0 Vdc to 18 Vdc

•

Capable of Driving Two Low–Power TTL Loads, One Low–Power

Schottky TTL Load or Two HTL Loads Over the Rated Temperature

Range

•

Chip Complexity: 488 FETs or 122 Equivalent Gates

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

(Voltages referenced to VSS)

Rating

Symbol

Value

Unit

DC Supply Voltage

VDD

– 0.5 to + 18

Vdc

Input Voltage, All Inputs

Vin

– 0.5 to VDD + 0.5

Vdc

DC Input Current, per Pin

Iin

mAdc

Power Dissipation, per Package†

500

Operating Temperature Range

– 55 to + 125

Storage Temperature Range

Tstg

– 65 to + 150

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

“P and D/DW” Packages: – 7.0 mW/C From 65

C To 125

C Ceramic

“L” Packages: – 12 mW/

C From 100

C To 125

SC SC(t–1) MR MR(t–1) Clock

Action

None

Reset

Start

Conversion

Start

Conversion

Continue

Conversion

Continue

Operation

TRUTH TABLES

MC14549B

X = Don’t Care

t–1 = State at Previous Clock

SC(t–1) EOC Clock

Action

None

Start

Conversion

Continue

Conversion

Continue

Conversion

Retain

Conversion

Result

Start

Conversion

MC14559B

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1995

REV 3

1/94

MC14549B

MC14559B

L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP

Plastic

MC14XXXBCL

Ceramic

MC14XXXBDW

SOIC

TA = – 55

to 125

C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

PIN ASSIGNMENT

VDD

EOC

VSS

Sout

* For MC14549B Pin 10 is MR input.

For MC14559B Pin 10 is FF input.

MOTOROLA CMOS LOGIC DATA

MC14549B MC14559B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS

(Voltages Referenced to VSS)

Characteristic

Symbol

VDD

Vdc

– 55

125

Unit

Characteristic

Symbol

Vdc

Min

Max

Min

Typ #

Max

Min

Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

VOL

5.0

—

0.05

—

0.05

—

0.05

Vdc

“1” Level

Vin = 0 or VDD

VOH

5.0

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

—

4.95

9.95

14.95

—

Vdc

Input Voltage #

“0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL

5.0

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

Vdc

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH

5.0

3.5

7.0

—

3.5

7.0

2.75

5.50

8.25

—

3.5

7.0

—

Vdc

Output Drive Current

(VOH = 2.5 Vdc)

Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH

5.0

– 1.2

– 0.25

– 0.62

– 1.8

—

– 1.0

– 0.2

– 0.5

– 1.5

– 1.7

– 0.36

– 0.9

– 3.5

—

– 0.7

– 0.14

– 0.35

– 1.1

—

mAdc

(VOL = 0.4 Vdc)

Sink

(VOL = 0.5 Vdc)

Q Outputs

(VOL = 1.5 Vdc)

IOL

5.0

1.28

3.2

8.4

—

1.02

2.6

6.8

1.76

4.5

17.6

—

0.72

1.8

4.8

—

mAdc

(VOL = 0.4 Vdc)

Sink

(VOL = 0.5 Vdc) Pin 5, 11 only

(VOL = 1.5 Vdc)

5.0

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

Input Current

Iin

—

0.1

—

0.00001

0.1

—

1.0

Adc

Input Capacitance

Cin

—

5.0

7.5

—

Quiescent Current

(Per Package)

(Clock = 0 V,

Other Inputs = VDD

or 0 V, Iout = 0

IDD

5.0

—

5.0

—

0.005

0.010

0.015

5.0

—

150

300

600

Adc

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

5.0

IT = (0.8

A/kHz) f + IDD

IT = (1.6

A/kHz) f + IDD

IT = (2.4

A/kHz) f + IDD

Adc

#Noise immunity specified for worst–case input combination.

Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V

2.0 V min @ VDD = 10 V

2.5 V min @ VDD = 15 V

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL = 50) VDDf

where: IT is in

A (per package), CL in pF, VDD in V, and f in kHz is input frequency.

** The formulas given are for the typical characteristics only at 25

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it

is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this

high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS

(Vin or

Vout)

VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).

MOTOROLA CMOS LOGIC DATA

MC14549B MC14559B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS*

(CL = 50 pF, TA = 25

Characteristic

Symbol

VDD

Min

Typ

Max

Unit

Output Rise Time

tTLH = (3.0 ns/pF) CL + 30 ns

tTLH = (1.5 ns/pF) CL + 15 ns

tTLH = (1.1 ns/pF) CL + 10 ns

tTLH

5.0

—

180

360

180

130

Output Fall Time

tTHL = (1.5 ns/pF) CL + 25 ns

tTHL = (0.75 ns/pF) CL + 12.5 ns

tTHL = (0.55 ns/pF) CL + 9.5 ns

tTHL

5.0

—

100

200

100

Propagation Delay Time

Clock to Q

tPLH, tPHL = (1.7 ns/pF) CL + 415 ns

tPLH, tPHL = (0.66 ns/pF) CL + 177 ns

tPLH, tPHL = (0.5 ns/pF) CL + 130 ns

Clock to Sout

tPLH, tPHL = (1.7 ns/pF) CL + 665 ns

tPLH, tPHL = (0.66 ns/pF) CL + 277 ns

tPLH, tPHL = (0.5 ns/pF) CL + 195 ns

Clock to EOC

tPLH, tPHL = (1.7 ns/pF) CL + 215 ns

tPLH, tPHL = (0.66 ns/pF) CL + 97 ns

tPLH, tPHL = (0.5 ns/pF) CL + 75 ns

tPLH,

tPHL

5.0

—

500

210

155

750

310

220

300

130

100

1000

420

310

1500

620

440

600

260

200

SC, D, FF or MR Setup Time

tsu

5.0

250

100

125

—

Clock Pulse Width

tWH(cl)

5.0

700

270

200

350

135

100

—

Pulse Width — D, SC, FF or MR

tWH

5.0

500

200

160

250

100

—

Clock Rise and Fall Time

tTLH,

tTHL

5.0

—

1.0

0.5

Clock Pulse Frequency

fcl

5.0

—

1.5

3.0

4.0

0.8

1.5

2.0

MHz

* The formulas given are for the typical characteristics only.

MOTOROLA CMOS LOGIC DATA

MC14549B MC14559B

SWITCHING TIME TEST CIRCUIT AND WAVEFORMS

fcl

tWH(cl)

50%

tsu

tWH(D)

tPHL

tPLH

50%

90%

10%

tTLH

tPLH

tTHL

90%

50%

10%

tTLH

Sout

NOTE: Pin 10 = VSS

VDD

VSS

EOC

Sout

FF(MR)

PROGRAMMABLE

PULSE

GENERATOR

TIMING DIAGRAM

* — Q8 is ninth–bit of serial information available from 8–bit register.

NOTE: Pin 10 = VSS

INH — Indicates Serial Out is inhibited low.

— Don’t care condition

ÉÉÉ

CLOCK

EOC

Sout

INH

INH Q7 Q6

Q8* INH

MOTOROLA CMOS LOGIC DATA

MC14549B MC14559B

OPERATING CHARACTERISTICS

Both the MC14549B and MC14559B can be operated in

either the “free run” or “strobed operation” mode for conver-

sion schemes with any number of bits. Reliable cascading

and/or recirculating operation can be achieved if the End of

Convert (EOC) output is used as the controlling function,

since with EOC = 0 (and with SC = 1 for MC14549B but

either 1 or 0 for MC14559B) no stable state exists under con-

tinual clocked operation. The MC14559B will automatically

recirculate after EOC = 1 during externally strobed operation,

provided SC = 1.

All data and control inputs for these devices are triggered

into the circuit on the positive edge of the clock pulse.

Operation of the various terminals is as follows:

C = Clock — A positive–going transition of the Clock is

required for data on any input to be strobed into the circuit.

SC = Start Convert — A conversion sequence is initiated

on the positive–going transition of the SC input on succeed-

ing clock cycles.

D = Data in — Data on this input (usually from a compara-

tor in A/D applications) is also entered into the circuit on a

positive–going transition of the clock. This input is Schmitt

triggered and synchronized to allow fast response and guar-

anteed quality of serial and parallel data.

MR = Master Reset (MC14549B Only) — Resets all out-

put to 0 on positive–going transitions of the clock. If removed

while SC = 0, the circuit will remain reset until SC = 1. This

allows easy cascading of circuits.

FF = Feed Forward (MC14559B Only) — Provides regis-

ter shortening by removing unwanted bits from a system.

For operation with less than 8 bits, tie the output

following

the least significant bit of the circuit to EOC. E.g., for a 6–bit

conversion, tie Q1 to FF; the part will respond as shown in

the timing diagram less two bit times. Not that Q1 and Q0 will

still operate and must be disregarded.

For 8–bit operation, FF is tied to VSS.

For applications with more than 8 but less than 16 bits, use

the basic connections shown in Figure 1. The FF input of the

MC14559B is used to shorten the setup. Tying FF directly to

the least significant bit used in the MC14559B allows EOC to

provide the cascading signal, and results in smooth transition

of serial information from the MC14559B to the MC14549B.

The Serial Out (Sout) inhibit structure of the MC14559B

remains inactive one cycle after EOC goes high, while Sout of

the MC14549B remains inhibited until the second clock cycle

of its operation.

Qn = Data Outputs — After a conversion is initiated the

Q’s on succeeding cycles go high and are then conditionally

reset dependent upon the state of the D input. Once condi-

tionally reset they remain in the proper state until the circuit is

either reset or reinitiated.

EOC = End of Convert — This output goes high on the

negative–going transition of the clock following FF = 1 (for

the MC14559B) or the conditional reset of Q0. This allows

settling of the digital circuitry prior to the End of Conversion

indication. Therefore either level or edge triggering can indi-

cate complete conversion.

Sout = Serial Out — Transmits conversion in serial fash-

ion. Serial data occurs during the clock period when the cor-

responding parallel data bit is conditionally reset. Serial Out

is inhibited on the initial period of a cycle, when the circuit is

reset, and on the second cycle after EOC goes high. This

provides efficient operation when cascaded.

Figure 1. 12–Bit Conversion Scheme

†Completion of conversion automatically re–initiates cycle in free run mode.

** Cascading using EOC guaranteed; no stable unfunctional state.

* FF allows EOC to activate as if in 4–stage register.

Q7 Q6 Q5 Q4

Q0 EOC

Sout

MC14559B

MSB

TO D/A AND PARALLEL DATA

••

FROM A/D

COMPARATOR

Q7 Q6 Q5

Sout

MC14549B

LSB

Q4 Q3 Q2 Q1 Q0 EOC

TO D/A AND

PARALLEL DATA

{

EXTERNAL STROBE

FREE RUN MODE

EXTERNAL

CLOCK

1/4 MC14001

SERIAL OUT

(CONTINUAL

UPDATE EVERY

13 CLOCK CYCLES)

MOTOROLA CMOS LOGIC DATA

MC14549B MC14559B

TYPICAL APPLICATIONS

Externally Controlled 6–Bit ADC (Figure 2)

Several features are shown in this application:

•

Shortening of the register to six bits by feeding the seventh

output bit into the FF input.

•

Continuous conversion, if a continuous signal is applied to

SC.

•

Externally controlled updating (the start pulse must be

shorter than the conversion cycle).

•

The EOC output indicating that the parallel data are valid

and that the serial output is complete.

Continuously Cycling 8–Bit ADC (Figure 3)

This ADC is running continuously because the EOC signal

is fed back to the SC input, immediately initiating a new cycle

on the next clock pulse.

Continuously Cycling 12–Bit ADC (Figure 4)

Because each successive approximation register (SAR)

has a capability of handling only an eight–bit word, two must

be cascaded to make an ADC with more than eight bits.

When it is necessary to cascade two SAR’s, the second

SAR must have a stable resettable state to remain in while

awaiting a subsequent start signal. However, the first stage

must not have a stable resettable state while recycling, be-

cause during switch–on or due to outside influences, the first

stage has entered a reset state, the entire ADC will remain in

a stable non–functional condition.

This 12–bit ADC is continuously recycling. The serial as

well as the parallel outputs are updated every thirteenth

clock pulse. The EOC pulse indicates the completion of

Figure 2. Externally Controlled 6–Bit ADC

TO DAC

Sout

Q7 Q6

MC14559B

EOC

Figure 3. Continuously Cycling 8–Bit ADC

TO DAC

Sout

Q7 Q6

MC14559B

EOC

MOTOROLA CMOS LOGIC DATA

MC14549B MC14559B

Q7 Q6 Q5

Sout

MC14549B

Q4 Q3 Q2 Q1 Q0 EOC

Sout

TO DAC

Q7 Q6 Q5

Sout

MC14559B

Q4 Q3 Q2 Q1 Q0

EOC

TO DAC

EOC

Figure 4. Continuously Cycling 12–Bit ADC

the 12–bit conversion cycle, the end of the serial output

word, and the validity of the parallel data output.

Externally Controlled 12–Bit ADC (Figure 5)

In this circuit the external pulse starts the first SAR and

simultaneously resets the cascaded second SAR. When Q4

of the first SAR goes high, the second SAR starts conver-

sion, and the first one stops conversion. EOC indicates that

the parallel data are valid and that the serial output is com-

plete. Updating the output data is started with every external

control pulse.

Additional Motorola Parts for Successive

Approximation ADC

Monolithic digital–to–analog converters — The

MC1408/1508 converter has eight–bit resolution and is avail-

able with 6, 7, and 8–bit accuracy. The amplifier–compara-

tor block — The MC1407/1507 contains a high speed

operational amplifier and a high speed comparator with ad-

justable window.

With these two linear parts it is possible to construct SA–

ADCs with an accuracy of up to eight bits, using as the regis-

ter one MC14549B or one MC14559B. An additional CMOS

block will be necessary to generate the clock frequency.

Additional information on successive approximation ADC

is found in Motorola Application Note AN–716.

Figure 5. Externally Controlled 12–Bit ADC

Q7 Q6 Q5

Sout

MC14549B

Q4 Q3 Q2 Q1 Q0 EOC

Sout

TO DAC

Q7 Q6 Q5

Sout

MC14559B

Q4 Q3 Q2 Q1 Q0

EOC

TO DAC

EOC