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S E M I C O N D U C T O R , I N C .

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The TQ8105/TQ8106 are SONET/SDH transceivers that integrate

multiplexing, demultiplexing, SONET/SDH framing, clock-synthesis PLL, and

enhanced line and clock diagnostic functions into a single monolithic device.

The TQ8106 is a pin-compatible upgrade of the TQ8105 that includes a

Clock and Data Recovery (CDR) function. The TQ8105 and TQ8106 allow

maximum flexibility in the selection of internal/external Clock and Data

Recovery, Opto-Electronic (O/E) Module, and Reference Clock Sources.

On-chip PLLs use external RC-based loop filters to allow custom tailoring of

loop response and support the wide range of reference clock frequencies

found in SONET/SDH/ATM systems. For transmit clock synthesis or for CDR,

the PLLs exceed ANSI, Bellcore, and ITU jitter specifications for systems

when combined with industry-typical O/E devices such as Sumitomo, AT&T,

HP, and AMP. The TQ8105/TQ8106 PLLs provide byte clocks and constant-

rate 38.88 MHz and 51.84 MHz, synthesized clock outputs, providing

clocking for UTOPIA and other system busses. Transmit data may also be

clocked into the devices with respect to the reference clock.

Operating from a single +5V supply, the TQ8105/TQ8106 provides fully

compliant functionality and performance, utilizing direct-connected PECL

levels (differential or single-ended) for high-speed I/O. As compared to AC-

coupled schemes, the direct-coupled connections reduce jitter and

switching-level offsets due to data patterns. The TQ8105/TQ8106 can also

provide direct connection to high-speed I/O utilizing ECL levels with a –5V

supply. Low-speed bus, control, and clock I/O utilize TTL levels. (An ECL/

PECL reference clock input is also provided; at 155.52 MHz the input should

be only PECL/ECL.) Output TTL pins can be tristated and may also be

configured for V

with a 3.3V supply connection.

TQ8105/8106

SONET/SDH

Overhead

Processor

TQ8105

TQ8106

SONET/SDH

Transceiver

Tx O/E

Rx O/E

with

CDR

SONET/SDH

Overhead

Processor

TQ8106

SONET/SDH

Transceiver

with CDR

Tx O/E

Rx O/E

Reference

Clock

SONET/SDH

Transceivers

Features

• Single-chip, byte-wide Mux,

Demux, Framer, and Tx clock-

synthesis PLL with enhanced

diagnostics

• TQ8106 includes monolithic

Clock and Data Recovery

• SONET/SDH/ATM compliant for

STS-12/STM-4 (622 Mb/s) or

STS-3/STM-1 (155 Mb/s) rates

• 155.52, 77.76, 51.84, 38.88, or

19.44 MHz reference clock inputs

with TTL, PECL, or ECL level

• 38.88 MHz and 51.84 MHz clock

outputs for UTOPIA as well as

byte clock rate (77.76 or 19.44 MHz)

• External RC-based loop filters

• Integrated loopbacks with

enhanced line and reference

clock diagnostics

• Direct-coupled standard, PECL,

high-speed I/O with ECL option

• Clean TTL interface to

PMC-Sierra devices

• 100-pin 14x14 mm JEDEC

plastic package

• +5V-only supply for PECL I/O

(–5.2V required for ECL I/O option)

• –40 to +125

C case operating

temperature

TQ8105/TQ8106

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Figure 1. TQ8105 Block Diagram

The combination of a thermally enhanced, 100-pin

JEDEC, metric, plastic package, the low-power

dissipation of the device, and the wide case-

temperature range permits operation without a heat

sink in most designs.

The TQ8106 uses the same pinout as the TQ8105 and

is compatible with it.

The TQ8105/TQ8106 provides comprehensive,

integrated, loopback functionality and enhanced line

and reference clock diagnostics required of SONET/

SDH systems, minimizing additional external circuitry.

TQ8105/TQ8106 diagnostics include:

• Loss of Reference clock detector (LOR) output to

indicate that the PLL Reference Clock is not toggling

• Lock Indicator (RLOCK), which permits monitoring

of the receiver clock frequency, flagging when the

frequency drifts beyond approximately 500 ppm

• Loss of Signal (LOS) detector output to indicate that

the incoming data stream has no data transitions in

128-bit periods

• ECL/PECL input (NSOL) to allow LOS from an O/E

module to force the data stream to all zeroes,

eliminating the need for external glue logic.

CKSRC(2:0)

MXD(7:0)

TXD

TXCK

RXD

RXCK

ECL/

PECL

I/O

Block

DVPP

Parallel

Serial

DXD(7:0)

LBM(1:0)

PH(1:0)

Loop

Back &

Retime

Block

LOS

Detect

VPP

VNN

FP1

REFCKE

REFCKT

MMS

Clock

Data

Clock

Data

Clock

Data

Clock

Data

Ext. Clk

OC3

Hold

NOE

LOS

DXSYNC

OOF

Serial

Parallel

Clock

Phase

TxBC

RxBC

Framer

Clock/8

LOR

NRESET

SDHCK

PLL Clock

Synthesizer

FP2

NSOL

SONETC

CLRLOS

Freq.

Lock

Detect

RLOCK

FRPWR

TQ8105

TQ8105/TQ8106

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Figure 2. TQ8106 Block Diagram

CKSRC(2:0)

MXD(7:0)

TXD

TXCK

RXD

RXCK

ECL/

PECL

I/O

Block

DVPP

Parallel

Serial

DXD(7:0)

LBM(1:0)

PH(1:0)

Loopback

& Retime

Block

LOS

Detect

VPP

VNN

FP1

REFCKE

REFCKT

MMS

Clock

Data

Clock

Data

Clock

Data

Clock

Data

Ext. Clk

OC3

Hold

NOE

LOS

DXSYNC

OOF

Serial

Parallel

Clock

Phase

TxBC

RxBC

Framer

Clock/8

LOR

NRESET

SDHCK

PLL Clock

Synthesizer

FP2

NSOL

SONETCK

CLRLOS

Freq.

Lock

Detect

RLOCK

FRPWR

Clock

& Data

Recovery

Data

Clock

NCDREN

CDRFP2

CDRFP1

CDRGND

CDRAVDD

Clock

Data

TQ8106

TQ8105/TQ8106

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Figure 3. 100-Pin Enhanced Plastic 14x14 mm Package Pinout

Table 1. Signal Descriptions (continues on next page)

Pin

Signal

Function

Description

VNN

–5.2V/Ground

ECL/PECL section power

No Connect

Do not connect

VPP

Ground/+5V

ECL/PECL Positive Supply (see Table 6B)

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

REFCKEN

ECL/PECL Input

Tx Ref. Clock or Bypass Clock, Complement

REFCKEP

ECL/PECL Input

Tx Ref. Clock or Bypass Clock, True

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

TXCKN

ECL/PECL Out

Transmit Clock, Complement

TXCKP

ECL/PECL Out

Transmit Clock, True

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

TXDN

ECL/PECL Out

Transmit Data, Complement

TXDP

ECL/PECL Out

Transmit Data, True

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

RXDN

ECL/PECL Input

Receive Data, Complement

RXDP

ECL/PECL Input

Receive Data, True

Note:

*TQ8106-specific signal

Note: *TQ8106-specific signal

TXDP

TXDN

DVPP

RXDP

DVPP

RXCKP

RXDN

DVPP

NSOL

VNN

GND

DVPP

RXCKN

DVPP

TXCKN

TXCKP

REFCKEP

VPP

REFCKEN

DXD2

DGND

DXD3

VCC

DXD1

DGND

DXD5

VCC

DXD4

VCC

DXD7

SVDD

VDD

DGND

DXD6

VCC

DXD0

DGND

DXSYNC

DGND

NC/CDRA

VDD*

VCC

RXBC

VDD

SVDD

VDD

LBM0

GND

NOE

GND

RLOCK

CLRLOS

CDRGND*/NC

LBM1

VCC

OOF

GND

LOS

DGND

MMS

OC3

NRESET

CKSRC2

CKSRC1

PH0

PH1

CKSRC0

VDD

SVDD

DGND

TXBC

VCC

SONETCK

VCC

MXD5

MXD4

MXD3

MXD6

MXD7

MXD0

MXD1

MXD2

LOR

DGND

SDHCK

AGND

FP2

VDD

FP1

REFCKT

100

GND

DVPP

NC/CDRFP2*

NC/CDRFP1*

VPP

GND

VNN

FRPWR

NCDREN*/NC

TQ8105/TQ8106

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Table 1. Signal Descriptions (continued)

Pin

Signal

Function

Description

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

RXCKP

ECL/PECL Input

Receive Clock, True (Ignored when CDR used)

RXCKN

ECL/PECL Input

Receive Clock, Complement (Ignored when CDR used)

DVPP

Ground/+5V

ECL/PECL Driver Return (see Table 6B)

VPP

Ground/+5V

ECL/PECL Positive Supply (see Table 6B)

NSOL

ECL/PECL Input

Loss of Signal — zeroes serial data in when low; RXBC=TXCK/8

VNN

–5.2V/Ground

ECL/PECL section power (see Table 6B)

NC/CDRFP1*

Analog Output

CDR Loop Filter Pin 1 — Charge Pump Out (ignored by TQ8105)

NC/CDRFP2*

Analog Input

CDR Loop Filter Pin 2 — VCO Tune (ignored by TQ8105)

GND

Core Ground

SVDD

+5V

Output Driver Internal Positive Supply

VDD

+5V

Core Positive Supply

CDRAVDD*

Analog +5V

TQ8106 CDR Analog +5V Supply

(not connected if CDR not used; ignored by TQ8105)

VCC

+5V/+3.3V

TTL Driver Positive Supply

RxBC

Tristate TTL Out

Demultiplexer Byte Clock

DGND

GND

TTL Driver Ground

DXSYNC

Tristate TTL Out

Frame Synchronization Signal

VCC

+5V/+3.3V

TTL Driver Positive Supply

DXD0

Tristate TTL Out

Demultiplexer Data Bit 0 (LSB)

DGND

GND

TTL Driver Ground

DXD1

Tristate TTL Out

Demultiplexer Data Bit 1

VCC

+5V/+3.3V

TTL Driver Positive Supply

DXD2

Tristate TTL Out

Demultiplexer Data Bit 2

DGND

GND

TTL Driver Ground

DXD3

Tristate TTL Out

Demultiplexer Data Bit 3

VCC

+5V/+3.3V

TTL Driver Positive Supply

DXD4

Tristate TTL Out

Demultiplexer Data Bit 4

DGND

GND

TTL Driver Ground

DXD5

Tristate TTL Out

Demultiplexer Data Bit 5

VCC

+5V/+3.3V

TTL Driver Positive Supply

DXD6

Tristate TTL Out

Demultiplexer Data Bit 6

DGND

GND

TTL Driver Ground

DXD7

Tristate TTL Out

Demultiplexer Data Bit 7 (MSB)

SVDD

+5V

Output Driver Internal Positive Supply

VDD

+5V

Core Positive Supply

NC/CDRGND*

GND

GND for TQ8106 to powerup CDR (ignored by TQ8105)

GND

Core Ground

FRPWR

TTL Input

Framer Power Control (power on when high)

OOF

TTL Input

Out-of-Frame: Initiates Frame Search/Bit Alignment

VCC

+5V/+3.3V

TTL Driver Positive Supply

LOS

Tristate TTL Output

Loss of Signal (high when > 128 bit periods without transitions)

DGND

GND

TTL Driver Ground

Note:

*TQ8106-specific signal

TQ8105/TQ8106

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Table 1. Signal Descriptions (continued)

Pin

Signal

Function

Description

CLRLOS

TTL Input

Active-high Clear LOS output

RLOCK

Tristate TTL Output

Receive Clock meets lock criteria when high

LBM1

TTL Input

Loopback Mode Control (see Table 3)

GND

Core Ground

LBM0

TTL Input

Loopback Mode Control (see Table 3)

VDD

+5V

Core Positive Supply

NOE

TTL Input

TTL tristate control (active low to enable)

GND

Core Ground

NRESET

TTL Input

Global Reset (active low)

OC3

TTL Input

OC3/OC12 Mode Select

MMS

TTL Input

Master/Slave Mode Control

CKSRC2

TTL Input

Clock Source Select (see Table 3)

CKSRC1

TTL Input

Clock Source Select (see Table 3)

CKSRC0

TTL Input

Clock Source Select (see Table 3)

PH1

TTL Input

TxBC Phase Select (see Table 3)

PH0

TTL Input

TxBC Phase Select (see Table 3)

VDD

+5V

Core Positive Supply

SVDD

+5V

Output Driver Internal Positive Supply

GND

Core Ground

MXD0

TTL Input

Multiplexer Data Bit 0 (LSB)

MXD1

TTL Input

Multiplexer Data Bit 1

MXD2

TTL Input

Multiplexer Data Bit 2

MXD3

TTL Input

Multiplexer Data Bit 3

MXD4

TTL Input

Multiplexer Data Bit 4

MXD5

TTL Input

Multiplexer Data Bit 5

MXD6

TTL Input

Multiplexer Data Bit 6

MXD7

TTL Input

Multiplexer Data Bit 7 (MSB)

VCC

+5V/+3.3V

TTL Driver Positive Supply

TxBC

Tristate TTL Out

Transmit Byte Clock

DGND

GND

TTL Driver Ground

SONETCK

Tristate TTL Out

51.84 MHz Clock Output

VCC

+5V/+3.3V

TTL Driver Positive Supply

SDHCK

Tristate TTL Out

38.88 MHz Clock Output

DGND

GND

TTL Driver Ground

LOR

Tristate TTL Out

Indicates Reference Clock is Absent

AGND

Analog Ground

VCO Analog Ground

FP2

Analog Output

Transmit PLL Loop Filter, Charge Pump Out

FP1

Analog Input

Transmit PLL Loop Filter, VCO Tune

AVDD

Analog +5V

VCO & Filter Analog VDD Supply

VDD

+5V

Core Positive Supply

REFCKT

TTL Input

Tx Reference Clock or Bypass Clock

GND

Core Ground

100

NC/NCDREN*

TTL Input

Internal Pull-up, Low = CDR receiver clock; Float = Pin 17/18 Rx Clk

(ignored by TQ8105)

Note:*TQ8106-specific signal

TQ8105/TQ8106

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Function Description

PLL

The TQ8105 & TQ8106 incorporate high-stability, low-

jitter Phase Locked Loops (PLLs) running at 2488.32

MHz. The PLLs use external surface mounted loop filters

consisting of an RC network as shown in the diagrams

that accompany the values shown in Table 2. Analog

design principles should be applied to the loop filter

portions of the circuit to ensure optimal jitter generation

performance. To reduce cross-coupling of clocks, both

CDR clocks and analog pins should be isolated from the

transmit PLL clock and analog pins. An analog ground

plane under the two capacitors and the resistor, along

with guards around the filter pins is excellent practice, as

is a well-filtered analog supply (AVDD) and a clean

analog ground (AGND). The loop filter values specified in

this preliminary data sheet may change.

Reference clock sourcing can be through a variety of

mechanisms. As shown in Table 3, the MMS pin

determines whether the device operates in Master

mode (where the PLL reference comes in on either a

TTL or PECL/ECL pin), or a Slave mode (where the PLL

reference is derived from the DEMUX high-speed line

clock input). If the external reference clock pins are

used, note that they are logical ORs and that the

unused pin should be tied to (a) GND for unused

REFCKT, or (b) REFCKEN should be tied to VPP for TTL

reference operation. The reference clock frequency can

be selected from any number of values, as indicated in

Table 3. Note that the PLL may be bypassed, allowing

use of an external clock reference.

Internal dividers determine the operating line rate, as

shown in Table 3. The device is capable of operating at

STM1/STS-3 or STM4/STS-12 rates. The transmit PLL

provides high performance and compliance with ITU/

Bellcore requirements found in the first-generation

TQ8101. The TQ8106 receiver's CDR can be disabled

for backwards pin-compatibility with the TQ8105. For

circuits not requiring the TQ8106's CDR, the CDR is

disabled by floating NCDREN (pin 100). Further, the CDR

section of the TQ8106 can be powered down by

disconnecting the CDRGND and CDRAVDD pins, thereby

reducing power consumption. If the TQ8106 CDR is not

used, the CDR filter pins may be left unconnected.

The transmit PLL also provides constant-rate 38.88 MHz

and 51.84 MHz TTL outputs which may be tristated. The

38.88 MHz & 51.84 MHz output may also be achieved by

using high-speed receiver timing in Clock Source Mode

011 (see Table 3).

Framer

The TQ8105 and TQ8106 provide a clean interface to

devices from PMC-Sierra and others. The Out-of-Frame

(OOF) input is a state (level)-initiated event, rather than

the edge-triggered event found on TriQuint’s first-

generation TQ8101 transceiver. When OOF is high, the

TQ8105/TQ8106 initiates a frame search for a serial bit

pattern of twelve A1s (three A1s in OC3 mode) followed

by three A2s. If a match occurs, the device realigns

byte boundaries and issues a logic high on the DXSYNC

pin during the third A2. In the absence of OOF, the

device will not realign byte boundaries, but will report

any bit-level matching of twelve A1s (three A1s in OC3

mode) followed by three A2s as a DXSYNC pulse.

Framer circuit power may be switched off by a TTL low on

the FRPWR pin, saving approximately 0.25W. No further

DXSYNC pulses will be issued, though bit alignment is

preserved in the demux. Note that the OOF and FRPWR

pins may be tied together, powering the framer only when

bit realignment is required (this is not recommended

practice, however, due to the inrush currents that may

result).

Loopbacks

As part of the TQ8105 and TQ8106 on-chip diagnostics,

four loopback modes are supported. These are selected

by the dedicated pins LBM0 and LBM1, as shown in

Table 3. The loopback modes are shown in Figure 5.

TQ8105/TQ8106

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Functional Description (continued)

Enhanced Diagnostics

The TQ8105 and TQ8106 incorporate on-chip clock

diagnostics, allowing fast, efficient fault detection and

isolation at the systems level.

The LOR (Loss Of Reference) output goes high when the

reference clock is absent. Note that this signal is not

latched and is only high when the reference clock is

missing. A reference clock is required for the TQ8106

CDR to function correctly.

The NSOL (Loss-of-signal input, active low, PECL/ECL

level) input allows the receiver to force zeroes onto the

demux outputs. A TTL-level signal may also be used for

NSOL if the resistor network, shown in the applications

section of this data sheet, is used. NSOL is useful when a

Loss Of Signal occurs on the receive optics, and a

quieting of invalid data is desired. The receiver is clocked

from the transmit clock when NSOL is active, and the

output RXBC clock is obtained from the transmit portion

of the TQ8105/TQ8106. This ensures compatibility with

devices, such as the PMC-Sierra S/UNI-622 and STTX

components, which may contain dynamic registers that

lose contents if clocks are removed. NSOL forces the

CDR to lock on REFCLK, except when in slave mode.

The LOS (Loss Of Signal) output goes high whenever

128-bit periods occur without transitions on the data

input to the demux. CLRLOS forces LOS low.

The RLOCK (Receiver LOCK) output goes low whenever the

signal on RXCK or the recovered clock drifts more than

500 ppm from the reference frequency. This output returns

high whenever the frequency accuracy is within 100 ppm.

Demux

The TQ8105/TQ8106 demultiplexer converts an NRZ

PECL/ECL data input, at either 155 Mb/s or 622 Mb/s,

and its corresponding PECL/ECL clock into a byte-parallel

78 MHz or 19 MHz tristatable TTL data bus. The timing is

shown in Figures 6 through 8. See the previous “Framer”

description for bit alignment details. The TQ8106 can

recover both clock and data from a NRZ data stream,

whereas the TQ8105 requires NRZ data and a recovered

clock.

Mux

The TQ8105/TQ8106 multiplexer converts a 78 MHz or

19 MHz byte-wide bus to a serial NRZ PECL/ECL data

stream. The bytes are clocked into the device with the

TXBC byte clock output. The timing is shown in Figures

6 through 8. Note that the TXBC output can be adjusted

in 90-degree phase increments to accommodate

variations in interface requirements. See Table 3 for

settings on the PH0 and PH1 pins controlling this

function. Data may also be clocked into the TQ8105/

TQ8106 by a 77 MHz reference, oscillator-clock source,

provided the data is within the timing limits shown in the

timing diagram labelled “Reference Clock Based

Transmit Timing.” The TQ8105 and TQ8106 do not

require the transmit latch found on earlier TQ8101

reference designs and are backwards compatible with

designs that have the latch incorporated.

High-Speed I/O and TTL Interfaces

The TQ8105/06P will operate with either PECL or ECL

operation on the high-speed I/O. With a single +5V

supply, the part interfaces directly with TTL and PECL

(Positive Emitter Coupled Logic). By providing an

additional -5.2V supply, the device’s high-speed I/O

becomes ECL, instead of PECL. The TQ8105/06S is

designed only for PECL high-speed I/0 operation with a

single +5V supply. The power supply connections for

PECL and ECL are shown in Table 6B.

The TTL outputs (Vcc) may be connected to either +5V or

+3.3V supplies. True TTL may be obtained with the +5V

connection; clamped operation, when connected to +3.3V,

ensures that maximum Voh levels do not exceed +3.3V.