WIRELESS COMMUNICATIONS DIVISION
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1
TQ3132
DATA SHEET
Low Current, 3V
Cellular Band
CDMA/AMPS LNA IC
Features
Small size: SOT23-8
Single 3V operation
Low-current operation
Gain Select
Mode Select
High IP3 performance
Few external components
50
Ω
Output
Applications
IS-95 CDMA Mobile Phones
AMPS Mobile Phones
Dual Mode CDMA Cellular applications
832-870MHz CDMA applications
Product Description
The TQ3132 is a low current, 3V, RF LNA IC designed specifically for Cellular band
CDMA/AMPS applications. It’s RF performance meets the requirements of products
designed to the IS-95 and AMPS standards. The TQ3132 is designed to be used
with the TQ5131 or TQ5132 (CDMA/AMPS mixer) which provides a complete CDMA
receiver for 800MHz dual-mode phones.
The LNA incorporates on-chip switches which determine CDMA, AMPS, and bypass
mode select. When used with the TQ5131 or TQ5132 (CDMA RFA/mixer), four gain
states are available. The RF output port is internally matched to 50
Ω
, greatly
simplifying the design and keeping the number of external components to a
minimum. The TQ3132 achieves good RF performance with low current
consumption, supporting long standby times in portable applications. Coupled with
the very small SOT23-8 package, the part is ideally suited for Cellular band mobile
phones.
Electrical Specifications
1
Parameter
Min
Typ
Max
Units
Frequency
832
894
MHz
Gain
13.0
dB
Noise Figure
1.4
dB
Input 3
rd
Order Intercept
8.0
dBm
DC supply Current
7.5
mA
Note 1: Test Conditions: Vdd=2.8V, Tc=25C, RF frequency=881MHz, CDMA High Gain state.
Control
Logic
C2
L1
GND
RF
IN
VDD
GND
RF
OUT
50 ohm
RF Out
Control
Logic
GND
C2
C3
TQ3132
Data Sheet
2
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Electrical Characteristics
Parameter
Conditions
Min.
Typ/Nom
Max.
Units
RF Frequency
832
881
894 MHz
CDMA Mode-High Gain
Gain
10.5
13.0
dB
Noise Figure
1.4
1.7
dB
Input IP3
6.0
8.0
dBm
LNA IN Return Loss (with external matching)
10
dB
LNA OUT Return Loss
10
dB
Supply Current
7.5
9.5
mA
Bypass Mode
Gain
-3.0
-2.0
dB
Noise Figure
2.0
3.0
dB
Input IP3
20.0
25.0
dBm
LNA IN Return Loss (with external matching)
10
dB
LNA OUT Return Loss
10
dB
Supply Current
1.0
2.5
mA
AMPS Mode
Gain
8.5
11.0
dB
Noise Figure
1.6
2.4
dB
Input IP3
2.0
4.0
dBm
LNA IN Return Loss (with external matching)
10
dB
LNA OUT Return Loss
10
dB
Supply Current
4.5
5.5
mA
Supply Voltage
2.7
2.8
3.3
V
Note 1: Test Conditions: Vdd=2.8V, RF=881MHz, T
C
= 25
°
C, unless otherwise specified.
Note 2: Min/Max limits are at +25
°
C case temperature, unless otherwise specified.
Absolute Maximum Ratings
Parameter
Value
Units
DC Power Supply
5.0
V
Power Dissipation
500
mW
Operating Temperature
-30 to 85
C
Storage Temperature
-60 to 150
C
Signal level on inputs/outputs
+20
dBm
Voltage to any non supply pin
+0.3
V
TQ3132
Data Sheet
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3
Typical Performance
Test Conditions, unless Otherwise Specified: Vdd=2.8V, Tc=+25C, RF=881MHz
CDMA High Gain Mode
Gain v Freq v Temp
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0
860
870
880
890
900
Frequency (MHz)
Gai
n (
dB)
-30C
+25C
+85C
CDMA High Gain Mode
IIP3 v Freq v Temp
7.0
7.5
8.0
8.5
9.0
9.5
10.0
860
870
880
890
900
Frequency (MHz)
IIP
3 (d
B
m
)
-30C
+25C
+85C
CDMA High Gain Mode
Noise Figure v Freq v Temp
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
860
870
880
890
900
Frequency (MHz)
Noi
se Fi
gur
e (
dB)
-30C
+25C
+85C
CDMA High Gain Mode
Idd v Vdd v Temp
4.00
5.00
6.00
7.00
8.00
9.00
10.00
2.5
2.7
2.9
3.1
3.3
3.5
Vdd (V)
Idd (
m
A)
-30C
+25C
+85C
AMPS Mode
Gain v Freq v Temp
9.0
9.5
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
860
870
880
890
900
Frequency (MHz)
Gai
n (
dB)
-30C
+25C
+85C
AMPS Mode
IIP3 v Freq v Temp
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
860
870
880
890
900
Frequency (MHz)
IIP
3 (d
B
m
)
-30C
+25C
+85C
TQ3132
Data Sheet
4
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AMPS Mode
Noise Figure v Freq v Temp
0.00
0.50
1.00
1.50
2.00
2.50
860
870
880
890
900
Frequency (MHz)
Noi
se Fi
gur
e (
dB)
-30C
+25C
+85C
AMPS Mode
Idd v Vdd v Temp
4.30
4.40
4.50
4.60
4.70
4.80
4.90
5.00
5.10
5.20
5.30
2.5
2.7
2.9
3.1
3.3
3.5
Vdd (V)
Idd (
m
A)
-30C
+25C
+85C
BYPASS Mode
Gain v Freq v Temp
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
860
870
880
890
900
Frequency (MHz)
G
ain
(d
B
)
-30C
+25C
+85C
BYPASS Mode
IIP3 v Freq v Temp
30.0
31.0
32.0
33.0
34.0
35.0
36.0
37.0
38.0
860
870
880
890
900
Frequency (MHz)
IIP
3 (d
B
m
)
-30C
+25C
+85C
BYPASS Mode
Noise Figure v Freq v Temp
0.00
0.50
1.00
1.50
2.00
2.50
860
870
880
890
900
Frequency (MHz)
Noi
se Fi
gur
e (
dB)
-30C
+25C
+85C
BYPASS Mode
Idd v Vdd v Temp
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.5
2.7
2.9
3.1
3.3
3.5
Vdd (V)
Idd (
m
A)
-30C
+25C
+85C
TQ3132
Data Sheet
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5
Application/Test Circuit
C2
LNA
GND
RF in
Vdd
GND
(paddle)
RF
out
GND
C3
Control
Logic
LNA input
LNA output
Vdd
R1
C2
C1
L1
Control Logic
Lbrd
Bill of Material for TQ3132 LNA Application/Test Circuit
Component
Reference Designator
Part Number
Value
Size
Manufacturer
Receiver IC
U1
TQ3132
SOT23-8
TriQuint Semiconductor
Capacitor
C1
3pF
0402
Capacitor
C2
15pF
0402
Resistor
R1
3.3
Ω
0402
Inductor
L1
15nH
0402
Inductor
Lbrd
See application note
TQ3132
Data Sheet
6
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TQ3132 Product Description
The TQ3132 is a miniature low noise amplifier in a small SOT-
23-8 package (2.9X2.8X1.14 mm) with operation at 2.8v. The
LNA specs are designed to be compatible with IS-98 Interim
Standard for Dual-Mode CDMA cellular systems. The LNA
features excellent linearity with small current consumption in all
modes. TQ3132 is configured in a cascode topology with
switching circuitry for the various CDMA output levels. A bias
control circuit sets the quiescent current for each mode and
ensures peak performance over process and temperature.
1
2
8
7
6
5
3
4
S2
S5
S3
S4
S6
C2
LNA
OUT
VDD
GND
LNA
GND
C3
LNA
IN
GND
Switch
Control
Bias
Control
S1
LNA Gain
Select
LNA Mode
Select
Figure 1. TQ3132 Functional Block Diagram
LNA Input Matching Network
Only three external components are needed to tune the LNA
(see Figure 2). The chip uses an external capacitor and inductor
for the input match to pin 3. The output is internally matched to
50 ohms at pin 6. In the TQ3132 the matching network is in the
signal path for all three modes: High Gain, AMPS, and Bypass.
Therefore, some experimentation is required to find the
matching network that provides a compromise between noise
figure and gain for all 3 modes. One could take the values used
on TriQuint’s evaluation board as a starting point (see Figure 2).
The input match will affect the output match to some degree as
well, so S22 should be monitored.
Shorted Board
Inductor
C3
C1
L1
C2
LNA_GS
LNA_MD
LNA_IN
2
1
4
5
6
8
3
7
TQ3132
C2
Vdd_LNA
LNA_OUT
Figure 2. TQ3132 Applications Circuit
Selecting the LNA Vdd Bypass Capacitor
A Vdd bypass capacitor is recommended close to pin 8. The
Vdd bypass capacitor has the largest effect on the LNA output
match. Because the input match affects the output match to
some degree as well, the process of picking the bypass
capacitor value involves some iteration. First, an input match is
selected to give adequate gain and noise figure. Then the
bypass capacitor is varied to give the best output match.
TriQuint’s evaluation board achieves a 2:1 VSWR with the
selected tuning components which allows direct connection to
the input of a SAW filter.
Logic Control Functions
The control lines can be toggled between high and low levels
using CMOS logic circuitry. A logic level high (C3) is applied to
pin 5 to change bias state from CDMA to Amps modes.
Similarly, a logic level high (C2) at pin 1 selects the gain step for
the amplifier. In the high gain mode, switches S1, S2, and S5
are closed, with switches S3 and S4 open. In the bypass mode,
switches S1, S2, and S5 are open, with switches S3 and S4
closed (see figure 1).
TQ3132
Data Sheet
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7
Table 1. TQ3132 Control lines C2, C3
TQ3132 LNA Mode
C2
C3
CDMA
High Gain (HG)
0
1
0
0
Bypassed
1
1
AMPS
0
1
Gain Control via Pin 4 Inductance
The source connection of the LNA cascode is brought out
separately through pin 4. This allows external degeneration of
the cascode by adding a small amount of PC board trace
inductance to pin 4. Thus some increase in IIP3 can be made
while reducing LNA gain. The total amount of inductance
present at the source of the cascode is equal to the bond wire
plus package plus external inductances. One should generally
use an external inductance such that gain in the High Gain
mode = 13.5dB. On the evaluation board the total PCB trace
inductance at pin 4 is approximately 2.57nH. In order to achieve
the desire gain, this board inductor should be shorted half way
of its total length which is equivalent to about 1.55nH.
Board Layout Recommendations
All ground pins should be kept close to the IC and have its own
via to the ground plane to minimize inductance. Most PC boards
for portable applications have thin dielectric layers and very
narrow line width which increase the board parasitic capacitance
and inductance. To minimize these effects when implementing a
matching network, it is recommended to relieve the ground
underneath pads carrying RF signals whenever possible.
RF input power levels for accurate test results
Because the CDMA devices have a number of gain states, it
important to make sure that IP3 measurements are not taken in
a state of compression. Additionally, using too low of a power
puts the IMD products too close to the noise floor for accurate
results. Additionally, the LNA in the bypass mode have OIP3 of
around 30dBm, which is higher than the IIP3 of common
spectrum analyzers in their preset configuration. We have
found that setting the spectrum analyzer attenuator to 20dB
allows for accurate measurement in that mode, and in all the
other modes.
TQ3132 Noise and S-Parameters Data
The following noise and S-parameter data was obtained using
TriQuint’s evaluation board. This information is intended to be
used as a guide to synthesize the LNA tuning network and find a
compromise between noise figure and gain for all modes.
Table 2. Gamma Opt analysis for TQ3132 High Gain Mode
Freq
(MHz)
Γ
Opt
< Angle
Fmin
(dB)
R noise
700
0.53
32.8
1.1
24.15
880
0.52
41.5
1.0
19.03
1000
0.49
42.6
1.1
17.98
Table 3. Gamma Opt analysis for TQ3132 AMPS Mode
Freq
(MHz)
Γ
Opt
< Angle
Fmin
(dB)
R noise
700
0.62
33.5
1.3
33.5
880
0.56
40.2
1.2
26.4
1000
0.53
41.9
1.3
25.1
TQ3132
Data Sheet
8
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2.0
1.0
0.5
-0.5
-1.0
-2.0
1.0
2.0
0.5
A
B
0.53 @ 32.8
z = 1.84 + j 1.45
y = 0.33 - j 0.26
Freq=700MHz
0.52 @ 41.5
z = 1.49 + j 1.4
y = 0.36 - j 0.34
Freq=880MHz
A
B
TQ3132 HG
Noise
Parameters
0.49 @ 42.6
z = 1.46 + j 1.29
y = 0.38 - j 0.34
Freq=1000MHz
C
C
Figure 3. TQ3132 CDMA High Gain Noise Parameters
2.0
1.0
0.5
-0.5
-1.0
-2.0
1.0
2.0
0.5
A
B
0.62 @ 33.5
z = 1.76 + j 1.95
y = 0.25 - j 0.28
Freq=700MHz
0.56 @ 40.2
z = 1.49 + j 1.6
y = 0.31 - j 0.33
Freq=880MHz
A
B
TQ3132 AMPS
Noise
Parameters
0.53 @ 41.9
z = 1.46 + j 1.44
y = 0.35 - j 0.34
Freq=1000MHz
C
C
Figure 4. TQ3132 CDMA AMPS Noise Parameters
TQ3132
Data Sheet
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Package Pinout
Pin Descriptions
Pin Name
Pin #
Description and Usage
C2
1
Control logic 2
GND
2
Ground, paddle
RF IN
3
RF input, off-chip matching required
LNA GND
4
Ground, LNA Source ground
C3
5
Control logic 3
RF OUT
6
RF output, no matching required
LNA GND
7
Ground
Vdd
8
LNA Vdd, typical 2.8V, C2 capacitor required
Control
Logic
C2
L1
GND
RF
IN
VDD
GND
RF
OUT
50 ohm
RF Out
Control
Logic
GND
C2
C3
TQ3132
Data Sheet
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Tel: (503) 615-9000
Email: info_wireless@tqs.com
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: info_wireless@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of
this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or
licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 2000 TriQuint Semiconductor, Inc. All rights reserved.
Revision A, April, 2000
10
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Package Type: SOT23-8 Plastic Package
DESIGNATION
DESCRIPTION
METRIC
ENGLISH
NOTE
A
OVERALL HEIGHT
1.20 +/-.25 mm
0.05 +/-.250 in
3
A1
STANDOFF
.100 +/-.05 mm
.004 +/-.002 in
3
b
LEAD WIDTH
.365 mm TYP
.014 in
3
c
LEAD THICKNESS
.127 mm TYP
.005 in
3
D
PACKAGE LENGTH
2.90 +/-.10 mm
.114 +/-.004 in
1,3
e
LEAD PITCH
.65 mm TYP
.026 in
3
E
LEAD TIP SPAN
2.80 +/-.20 mm
.110 +/-.008 in
3
E1
PACKAGE WIDTH
1.60 +/-.10 mm
.063 +/-.004 in
2,3
L
FOOT LENGTH
.45 +/-.10 mm
.018 +/-.004 in
3
Theta
FOOT ANGLE
1.5 +/-1.5 DEG
1.5 +/-1.5 DEG
Notes
1. The package length dimension includes allowance for mold mismatch and flashing.
2. The package width dimension includes allowance for mold mismatch and flashing.
3. Primary dimensions are in metric millimeters. The English equivalents are calculated and subject to rounding error.
E
L
A1
b
e
FUSED LEAD
c
A
Note 1
PIN 1
E1
Note 2
θ
DIE