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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

REV 0

Motorola, Inc. 1995

10/95

Product Preview

8-Bit Serial or Parallel-Input/

Serial-Output Shift Register

High–Performance Silicon–Gate CMOS

The MC54/74HC165A is identical in pinout to the LS165. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This device is an 8–bit shift register with complementary outputs from the

last stage. Data may be loaded into the register either in parallel or in serial

form. When the Serial Shift/Parallel Load input is low, the data is loaded

asynchronously in parallel. When the Serial Shift/Parallel Load input is high,

the data is loaded serially on the rising edge of either Clock or Clock Inhibit

(see the Function Table).

The 2–input NOR clock may be used either by combining two independent

clock sources or by designating one of the clock inputs to act as a clock

inhibit.

•

Output Drive Capability: 10 LSTTL Loads

•

Outputs Directly Interface to CMOS, NMOS, and TTL

•

Operating Voltage Range: 2 to 6 V

•

Low Input Current: 1

•

High Noise Immunity Characteristic of CMOS Devices

•

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•

Chip Complexity: 286 FETs or 71.5 Equivalent Gates

FUNCTION TABLE

Inputs

Internal Stages

Output

Operation

Serial Shift/

Parallel Load

Clock

Inhibit

A – H

Operation

…

Asynchronous Parallel Load

QAn

QGn

Serial Shift via Clock

QAn

QGn

Serial Shift via Clock Inhibit

No Change

Inhibited Clock

No Change

No Clock

X = don’t care

QAn – QGn = Data shifted from the preceding stage

This document contains information on a product under development. Motorola reserves the right to change or

discontinue this product without notice.

MC54/74HC165A

PIN ASSIGNMENT

CLOCK INHIBIT

VCC

CLOCK

SERIAL SHIFT/

PARALLEL LOAD

GND

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXAD

MC74HCXXXADT

Ceramic

Plastic

SOIC

TSSOP

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

LOGIC DIAGRAM

PIN 16 = VCC

PIN 8 = GND

PARALLEL

DATA

INPUTS

SERIAL

DATA

INPUT

SERIAL SHIFT/

PARALLEL LOAD

CLOCK

CLOCK INHIBIT

SERIAL

DATA

OUTPUTS

MC54/74HC165A

MOTOROLA

High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎÎ

750

500

450

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

(Ceramic DIP)

ÎÎÎÎÎÎ

260

300

ÎÎÎ

* Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

TSSOP Package: – 6.1 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time

VCC = 2.0 V

(Figure 1)

VCC = 3.0 V

VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

600

500

400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

0.5

0.9

1.35

1.80

ÎÎÎÎ

0.5

0.9

1.35

1.80

ÎÎÎÎ

0.5

0.9

1.35

1.80

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

2.4 mA

|Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

3.0

4.5

6.0

ÎÎÎ

2.48

3.98

5.48

ÎÎÎÎ

2.34

3.84

5.34

ÎÎÎÎ

2.20

3.70

5.20

ÎÎÎ

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or Vout)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC165A

High–Speed CMOS Logic Data

DL129 — Rev 6

MOTOROLA

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎ

Unit

ÎÎÎÎ

125

ÎÎÎÎ

ÎÎÎ

– 55 to

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

2.4 mA

|Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

3.0

4.5

6.0

ÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.40

ÎÎÎ