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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

REV 7

Motorola, Inc. 1995

10/95

8-Input Data Selector/

Multiplexer With Data and

Address Latches and

3-State Outputs

High–Performance Silicon–Gate CMOS

The MC54/74HC354 is identical in pinout to the LS354. The device

inputs are compatible with Standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

The HC354 selects one of eight latched binary Data Inputs, as deter-

mined by the Address Inputs. The information at the Data Inputs is stored

in the transparent 8–bit Data Latch when the Data–Latch Enable pin is

held high. The Address information may be stored in the transparent

Address Latch, which is enabled by the active–high Address–Enable pin.

The device outputs are placed in high–impedance states when Output

Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low.

The HC354 has a clocked Data Latch that is not transparent.

•

Output Drive Capability: 15 LSTTL Loads

•

Outputs Directly Interface to CMOS, NMOS and TTL

•

Operating Voltage Range: 2 to 6V

•

Low Input Current: 1

•

High Noise Immunity Characteristic of CMOS Devices

•

In Compliance With the JEDEC Standard No. 7A Requirements

•

Chip Complexity: 326 FETs or 81.5 Equivalent Gates

LOGIC DIAGRAM

8–BIT

DATA

LATCH

(TRANS–

PARENT)

8–BIT

MULTI–

PLEXER

DATA

INPUTS

3–STATE

OUTPUT

CONTROL

3–STATE

DATA

OUTPUTS

DATA–LATCH

ENABLE

ADDRESS

INPUTS

ADDRESS–LATCH

ENABLE

OE1

OE2

OE3

OUTPUT

ENABLES

ADDRESS

LATCH

(TRANS–

PARENT)

PIN 20 = VCC

PIN 10 = GND

MC54/74HC354

VCC

OE3

OE2

OE1

Data–Latch

Enable

Address–Latch

Enable

GND

Pinout: 20–Lead Package (Top View)

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCXXXJ

MC74HCXXXN

MC74HCXXXDW

Ceramic

Plastic

SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

MC54/74HC354

MOTOROLA

High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 1.5 to VCC + 1.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic or Ceramic DIP†

SOIC Package†

ÎÎÎÎÎÎ

750

500

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature Range

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP or SOIC Package

Ceramic DIP

ÎÎÎÎÎÎ

260

300

ÎÎÎ

* Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature Range, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise/Fall Time

VCC = 2.0 V

(Figure 1)

VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

DC CHARACTERISTICS

(Voltages Referenced to GND)

Symbol

Parameter

Condition

VCC

Guaranteed Limit

Unit

Symbol

Parameter

Condition

VCC

–55 to 25

≤

125

Unit

VIH

Minimum High–Level Input Voltage

Vout = 0.1V or VCC –0.1V

|Iout|

≤

2.0

4.5

6.0

1.50

3.15

4.20

1.50

3.15

4.20

1.50

3.15

4.20

VIL

Maximum Low–Level Input Voltage

Vout = 0.1V or VCC – 0.1V

|Iout|

≤

2.0

4.5

6.0

0.3

0.9

1.2

0.3

0.9

1.2

0.3

0.9

1.2

VOH

Minimum High–Level Output

Voltage

Vin = VIH or VIL

|Iout|

≤

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin =VIH or VIL

|Iout|

≤

6.0mA

|Iout|

≤

7.8mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

VOL

Maximum Low–Level Output

Voltage

Vin = VIH or VIL

|Iout|

≤

2.0

4.5

6.0

0.1

Vin = VIH or VIL

|Iout|

≤

6.0mA

|Iout|

≤

7.8mA

4.5

6.0

0.26

0.33

0.40

Iin

Maximum Input Leakage Current

Vin = VCC or GND

6.0

0.1

1.0

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or Vout)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC354

High–Speed CMOS Logic Data

DL129 — Rev 6

MOTOROLA

DC CHARACTERISTICS

(Voltages Referenced to GND)

Symbol

Unit

Guaranteed Limit

VCC

Condition

Parameter

Symbol

Unit

≤

125

≤

–55 to 25

VCC

Condition

Parameter

IOZ

Maximum Three–State Leakage

Current

Output in High–Impedance State

Vin = VIL or VIH

Vout = VCC or GND

6.0

0.5

5.0

10.0

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0

6.0

160

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS

(CL = 50 pF, Input tr = tf = 6 ns)

Symbol

Parameter

VCC

Guaranteed Limit

Unit

Symbol

Parameter

VCC

–55 to 25

≤

125

Unit

tPLH,

tPHL

Maximum Propagation Delay, D0–D7 to Y or Y

(Figures 2 and 6)

2.0

4.5

6.0

210

265

315

tPLH,

tPHL

Maximum Propagation Delay, Data–Latch Enable to Y or Y

(Figures 3 and 6)

2.0

4.5

6.0

260

325

390

tPLH,

tPHL

Maximum Propagation Delay, A0–A2 to Y or Y

(Figures 2 and 6)

2.0

4.5

6.0

270

340

405

tPLH,

tPHL

Maximum Propagation Delay, Address–Latch Enable to Y or Y

(Figures 3 and 6)

2.0

4.5

6.0

270

340

405

tPLZ,

tPHZ

Maximum Propagation Delay, OE1–OE3 to Y or Y

(Figures 4 and 7)

2.0

4.5

6.0

160

200

240

tPZL,

tPZH

Maximum Propagation Delay, OE1–OE3 to Y or Y

(Figures 4 and 7)

2.0

4.5

6.0

125

155

190

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 6)

2.0

4.5

6.0

Cin

Maximum Input Capacitance

Cout

Maximum Three–State Output Capacitance (Output in High Impedance

State)

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Package)*

Typical @ 25

C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Package)*

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC354

MOTOROLA

High–Speed CMOS Logic Data

DL129 — Rev 6

PIN DESCRIPTIONS

D0–D7 (Pins 8–1) DATA INPUTS

These eight data bits are stored in a transparent latch when

the Data–Latch Enable pin is active (high). Once enabled,

changing inputs will not change the contents of the latch.

A0, A1, A2 (Pins 14,13,12) ADDRESS INPUTS

Selects which data bit stored in the Data Latch is routed to

the outputs Y and Y.

DATA–LATCH ENABLE (Pin 9)

The latch is transparent to D0–D7 when enable is inactive

(low). The Data–Latch contents are unaffected when enable

is held active (high).

ADDRESS–LATCH ENABLE (Pin 11)

The latch is transparent to A0, A1 and A2 when enable is

inactive (low). The Address–Latch contents are unaffected

when enable is held active (high).

OE1, OE2, OE3 (Pins 15,16,17) OUTPUT ENABLES

Any of the output enable pins inactive (OE1=High or

OE2=High or OE3=Low) causes the outputs (Y and Y) to be

in high–impedance states.

Y, Y (Pins 19,18)

These 3–state outputs (when not 3–stated) represent the

data bit in the Data Latch selected by the Address Latch.

TIMING REQUIREMENTS

(Input tr = tf = 6 ns)

VCC

Guaranteed Limit

Symbol

Parameter

VCC

–55 to 25

≤

125

Unit

tsu

Minimum Setup Time, D0–D7 to Data–Latch Enable

(Figure 5)

2.0

4.5

6.0

tsu

Minimum Setup Time, A0–A2 to Address–Latch Enable

(Figure 5)

2.0

4.5

6.0

Minimum Hold Time, Data–Latch Enable to D0–D7

(Figure 5)

2.0

4.5

6.0

Minimum Hold Time, Address–Latch Enable to A0–A2

(Figure 5)

2.0

4.5

6.0

Minimum Pulse Width, Data–Latch Enable

(Figure 3)

2.0

4.5

6.0

100

120

Minimum Pulse Width, Address–Latch Enable

(Figure 3)

2.0

4.5

6.0

100

120

tr, tf

Maximum Input Rise and Fall Times

(Figure 1)

2.0

4.5

6.0

1000

500

400

1000

500

400

1000

500

400

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).