DATA SHEET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jun 04
INTEGRATED CIRCUITS
74HC/HCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
1998 Jun 04
2
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
FEATURES
•
8-bit serial input
•
8-bit serial or parallel output
•
Storage register with 3-state outputs
•
Shift register with direct clear
•
100 MHz (typ) shift out frequency
•
Output capability:
– parallel outputs; bus driver
– serial output; standard
•
I
CC
category: MSI.
APPLICATIONS
•
Serial-to-parallel data conversion
•
Remote control holding register.
DESCRIPTION
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “595” is an 8-stage serial shift register with a storage
register and 3-state outputs. The shift register and storage
register have separate clocks.
Data is shifted on the positive-going transitions of the
SH
CP
input. The data in each register is transferred to the
storage register on a positive-going transition of the ST
CP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (D
S
) and a serial
standard output (Q
7
’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µ
W):
P
D
= C
PD
×
V
CC
2
×
f
i
+ ∑
(C
L
×
V
CC
2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC
2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
; for HCT the condition is V
I
= GND to V
CC
−
1.5 V.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
HC
HCT
t
PHL
/t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
SH
CP
to Q
7
’
16
21
ns
ST
CP
to Q
n
17
20
ns
MR to Q
7
’
14
19
ns
f
max
maximum clock frequency SH
CP
, ST
CP
100
57
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per package
notes 1 and 2
115
130
pF
1998 Jun 04
3
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
ORDERING INFORMATION
PINNING
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
74HC595N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HC595D
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
74HC595DB
SSOP16
plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
74HC595PW
TSSOP16
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
74HCT595N
DIP16
plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
74HCT595D
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
SYMBOL
PIN
DESCRIPTION
Q
0
to Q
7
15, 1 to 7
parallel data output
GND
8
ground (0 V)
Q
7
’
9
serial data output
MR
10
master reset (active LOW)
SH
CP
11
shift register clock input
ST
CP
12
storage register clock input
OE
13
output enable (active LOW)
D
S
14
serial data input
V
CC
16
positive supply voltage
Fig.1 Pin configuration.
handbook, halfpage
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
Q0
DS
GND
STCP
SHCP
VCC
OE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
595
MLA001
MR
Fig.2 Logic symbol.
handbook, halfpage
OE
MR
9
15
1
2
3
4
5
6
7
13
10
14
11
12
MLA002
Q1
Q0
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
DS
STCP
SHCP
1998 Jun 04
4
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Fig.3 IEC logic symbol.
handbook, halfpage
MSA698
15
9
1
2
3
4
5
6
7
1D
2D
C1/
10
11
14
C2
12
13
EN3
SRG8
R
3
OE
MR
Q1
Q0
Q2
Q3
Q4
Q5
Q6
Q7
Q7'
DS
STCP
SHCP
Fig.4 Functional diagram.
handbook, full pagewidth
STCP
DS
SHCP
MR
Q7'
8-STAGE SHIFT REGISTER
8-BIT STORAGE REGISTER
14
11
10
12
9
OE
3-STATE OUTPUTS
Q1
Q2
Q3
Q5
Q6
Q7
Q4
Q0
15
1
2
3
4
5
6
7
13
MLA003
1998 Jun 04
5
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Fig.5 Logic diagram.
handbook, full pagewidth
STAGE 0
STAGES 1 TO 6
STAGE 7
FF0
D
CP
Q
R
LATCH
D
CP
Q
FF7
D
CP
Q
R
LATCH
D
CP
Q
MLA010
D
Q
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Q7'
Q0
DS
STCP
SHCP
OE
MR
1998 Jun 04
6
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
FUNCTION TABLE
Notes
1. H = HIGH voltage level; L = LOW voltage level
↑
= LOW-to-HIGH transition;
↓
= HIGH-to-LOW transition
Z = high-impedance OFF-state; NC = no change
X = don’t care.
INPUTS
OUTPUTS
FUNCTON
SH
CP
ST
CP
OE
MR
D
S
Q
7
’
Q
N
X
X
L
L
X
L
NC
a LOW level on MR only affects the shift registers
X
↑
L
L
X
L
L
empty shift register loaded into storage register
X
X
H
L
X
L
Z
shift register clear. Parallel outputs in high-impedance
OFF-state
↑
X
L
H
H
Q
6
’
NC
logic high level shifted into shift register stage 0. Contents
of all shift register stages shifted through, e.g. previous
state of stage 6 (internal Q
6
’) appears on the serial output
(Q
7
’)
X
↑
L
H
X
NC
Q
n
’
contents of shift register stages (internal Q
n
’) are
transferred to the storage register and parallel output
stages
↑
↑
L
H
X
Q
6
’
Q
n
’
contents of shift register shifted through. Previous
contents of the shift register is transferred to the storage
register and the parallel output stages.
1998 Jun 04
7
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Fig.6 Timing diagram.
handbook, full pagewidth
high-impedance OFF-state
STCP
DS
SHCP
MR
OE
Q1
Q0
Q7'
Q6
Q7
MLA005 - 1
1998 Jun 04
8
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see chapter
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: parallel outputs, bus driver, serial output, standard I
CC
category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITION
+
25
−
40 to
+
85
−
40 to
+
125
V
CC
(V)
WAVEFORMS
min
typ
max
min
max
min
max
t
PHL
/t
PLH
propagation delay
SH
CP
to Q
7
’
−
52
160
−
200
−
240
ns
2.0
Fig.7
−
19
32
−
40
−
48
4.5
−
15
27
−
34
−
41
6.0
t
PHL
/t
PLH
propagation delay
ST
CP
to Q
n
−
55
175
−
220
−
265
ns
2.0
Fig.8
−
20
35
−
44
−
53
4.5
−
16
30
−
37
−
45
6.0
t
PHL
propagation delay
MR to Q
7
’
−
47
175
−
220
−
265
ns
2.0
Fig.10
−
17
35
−
44
−
53
4.5
−
14
30
−
37
−
45
6.0
t
PZH
/t
PZL
3-state output
enable time
OE to Q
n
−
47
150
−
190
−
225
ns
2.0
Fig.11
−
17
30
−
38
−
45
4.5
−
14
26
−
33
−
38
6.0
t
PHZ
/t
PLZ
3-state output
disable time
OE to Q
n
−
41
150
−
190
−
225
ns
2.0
Fig.11
−
15
30
−
38
−
45
4.5
−
12
26
−
33
−
38
6.0
t
W
shift clock pulse
width HIGH or
LOW
75
17
−
95
−
110
−
ns
2.0
Fig.7
15
6
−
19
−
22
−
4.5
13
5
−
16
−
19
−
6.0
t
W
storage clock
pulse width HIGH
or LOW
75
11
−
95
−
110
−
ns
2.0
Fig.8
15
4
−
19
−
22
−
4.5
13
3
−
16
−
19
−
6.0
t
W
master reset
pulse width LOW
75
17
−
95
−
110
−
ns
2.0
Fig.10
15
6.0
−
19
−
22
−
4.5
13
5.0
−
16
−
19
−
6.0
t
su
set-up time D
S
to
SH
CP
50
11
−
65
−
75
−
ns
2.0
Fig.9
10
4.0
−
13
−
15
−
4.5
9.0
3.0
−
11
−
13
−
6.0
t
su
set-up time SH
CP
to ST
CP
75
22
−
95
−
110
−
ns
2.0
Fig.8
15
8
−
19
−
22
−
4.5
13
7
−
16
−
19
−
6.0
1998 Jun 04
9
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
t
h
hold time D
S
to
SH
CP
3
−
6
−
3
−
3
−
ns
2.0
Fig.9
3
−
2
−
3
−
3
−
4.5
3
−
2
−
3
−
3
−
6.0
t
rem
removal time MR
to SH
CP
50
−
19
−
65
−
75
−
ns
2.0
Fig.10
10
−
7
−
13
−
15
−
4.5
9
−
6
−
11
−
13
−
6.0
f
max
maximum clock
pulse frequency
SH
CP
or ST
CP
9
30
−
4.8
−
4
−
MHz
2.0
Figs 7 and 8
30
91
−
24
−
20
−
4.5
35
108
−
28
−
24
−
6.0
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITION
+
25
−
40 to
+
85
−
40 to
+
125
V
CC
(V)
WAVEFORMS
min
typ
max
min
max
min
max
1998 Jun 04
10
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see chapter
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: parallel outputs, bus driver; serial output, standard I
CC
category: MSI.
Note to HCT types
The value of additional quiescent supply current (
∆
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
∆
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
INPUT
UNIT LOAD COEFFICIENT
D
S
0.25
MR
1.50
SH
CP
1.50
ST
CP
1.50
OE
1.50
1998 Jun 04
11
Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
SYMBOL PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITION
+
25
−
40 to
+
85
−
40 to
+
125
V
CC
(V)
WAVEFORMS
min
typ
max
min
max
min
max
t
PHL
/ t
PLH
propagation delay
SH
CP
to Q
7
’
−
25
42
−
53
−
63
ns
4.5
Fig.7
t
PHL
/ t
PLH
propagation delay
ST
CP
to Q
n
−
24
40
−
50
−
60
ns
4.5
Fig.8
t
PHL
propagation delay
MR to Q