MC44817/17B
SEMICONDUCTOR
TECHNICAL DATA
TV AND VCR
PLL TUNING CIRCUITS
WITH 1.3 GHz PRESCALER
AND 3–WIRE BUS
PIN CONNECTIONS
Order this document by MC44817/D
1
16
15
14
13
12
11
10
9
2
3
4
5
6
7
8
DA
CL
XTAL
VCC2 33 V
VCC1 5.0 V
HF In
EN
Gnd
D SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO–16)
16
1
Amp In
VTUN
Lock
VCC3 12 V
B3
B2
B1
B0
(Top View)
1
MOTOROLA ANALOG IC DEVICE DATA
PLL Tuning Circuits
with 3-Wire Bus
The MC44817/17B are tuning circuits for TV and VCR tuner applications.
They contain on one chip all the functions required for PLL control of a VCO.
The integrated circuits also contain a high frequency prescaler and thus can
handle frequencies up to 1.3 GHz.
The MC44817 has programmable 512/1024 reference divider while the
MC44817B has a fixed reference divider of 1024.
The MC44817/17B are manufactured on a single silicon chip using
Motorola’s high density bipolar process, MOSAIC
™
(Motorola Oxide Self
Aligned Implanted Circuits).
•
Complete Single Chip System for MPU Control (3–Wire Bus). Data and
Clock Inputs are IIC Bus Compatible
•
Divide–by–8 Prescaler Accepts Frequencies up to 1.3 GHz
•
15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz
•
Reference Divider: Programmable for Division Ratios 512 and 1024.
The MC44817B has a Fixed 1024 Reference Divider
•
Tri–State Phase/Frequency Comparator
•
Operational Amplifier for Direct Tuning Voltage Output (30 V)
•
Four Integrated PNP Band Buffers for 40 mA (VCC1 to 14.4 V)
•
Output Options for the Reference Frequency and the
Programmable Divider
•
Bus Protocol for 18 or 19 Bit Transmission
•
Extra Protocol for 34 Bit for Test and Further Features
•
High Sensitivity Preamplifier
•
Circuit to Detect Phase Lock
•
Fully ESD Protected
MOSAIC is a trademark of Motorola, Inc.
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
MC44817D
TA = – 20
°
to + 80
°
C
SO–16
MC44817BD
TA = – 20
°
to + 80
°
C
SO–16
©
Motorola, Inc. 1996
Rev 1
MC44817/17B
2
MOTOROLA ANALOG IC DEVICE DATA
Representative Block Diagram
This device contains 3,204 active transistors.
Gnd
Test
Logic
Buffers
Latches
P–On
Reset
3–Wire Bus
Receiver
Latches
Phase
Comp
Ref
Divider
Osc
Latch Control
Program Divider
15 Bit
Latches B
Latches A
Shift Register
15 Bit
÷
8
Prescaler
Preamp 2
Preamp 1
DTB2
POR
Operational
Amplifier
2.7 V
20 k
DTB1
CL
Data
RL
DTF
Fout
TDI
Fout
Fref
T5
T0
…
T3
T6
T4
4
6
15
10
11
12
13
14
5
6
7
5.0 V
Fout
Fref
9
16
1
2
8
EN
Data
Clock
HF Input
VCC1
VCC3
VTUN
VCC2
Bands Out 30 mA
(40 mA at 0
°
to 80
°
C)
Amp In
Lock
XTAL
B3 B2 B1 B0
DTS, EN
512/1024
B = 1024 Only
4
15
3
12 V
MAXIMUM RATINGS
(TA = 25
°
C, unless otherwise noted.)
Rating
Pin
Value
Unit
Power Supply Voltage (VCC1)
7
6.0
V
Band Buffer “Off” Voltage
10–13
14.4
V
Band Buffer “On” Current
10–13
50
mA
Band Buffer – Short Circuit Duration (0 to VCC3) (Note 2)
10–13
Continuous
–
Operational Amplifier Power Supply Voltage (VCC2)
6
40
V
Operational Amplifier Short Circuit Duration (0 to VCC2)
5
Continuous
–
Power Supply Voltage (VCC3)
14
14.4
V
Storage Temperature
–
– 65 to +150
°
C
Operating Temperature Range
–
– 20 to +80
°
C
Band Buffer Operation (Note 1) at 50 mA each Buffer
All Buffers “On” Simultaneously
10–13
10
sec
Operational Amplifier Output Voltage
5
VCC2
V
RF Input Level (10 MHz to 1.3 GHz)
–
1.5
Vrms
NOTES: 1. At VCC3 = VCC1 to 14.4 V and TA = – 20
°
to + 80
°
C.
2. At VCC3 = VCC1 to 14.4 V and TA = – 20
°
to + 80
°
C one buffer “On” only.
MC44817/17B
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS
(VCC1 = 5.0 V, VCC2 = 33 V, VCC3 = 12 V, TA = 25
°
C, unless otherwise noted.)
Characteristic
Pin
Min
Typ
Max
Unit
VCC1 Supply Voltage Range
7
4.5
5.0
5.5
V
VCC1 Supply Current (VCC1 = 5.0 V)
7
–
37
50
mA
VCC2 Supply Voltage Range
6
25
–
37
V
VCC2 Supply Current (Output Open)
6
–
1.5
3.5
mA
Band Buffer Leakage Current when “Off” at 12 V
10–13
–
0.01
1.0
µ
A
Band Buffer Saturation Voltage when “On” at 30 mA
10–13
–
0.15
0.3
V
Band Buffer Saturation Voltage when “On” at 40 mA
only for 0
°
to 80
°
C
10–13
–
0.2
0.5
V
Data/Clock/Enable Current at 0 V
1, 2, 16
–10
–
0
µ
A
Data/Clock/Enable Current at 5.0 V
1, 2, 16
0
–
1.0
µ
A
Data/Clock/Enable Input Voltage Low
1, 2, 16
–
–
1.5
V
Data/Clock/Enable Input Voltage High
1, 2, 16
3.0
–
–
V
Clock Frequency Range
2
–
–
100
kHz
Oscillator Frequency Range
3
3.15
3.2
4.05
MHz
Operational Amplifier Internal Reference Voltage
–
2.0
2.75
3.2
V
Operational Amplifier Input Current
4
–15
0
15
nA
DC Open Loop Voltage Gain
–
100
250
–
V/V
Gain Bandwidth Product (CL = 1.0 nF)
–
0.3
–
–
MHz
Vout Low, Sinking 50
µ
A
5
–
0.2
0.4
V
Vout High, Sourcing 10
µ
A, VCC2 – Vout
5
–
0.2
0.5
V
Phase Comparator Tri–State Current
4
–15
0
15
nA
Charge Pump High Current of Phase Comparator
4
30
50
85
µ
A
Charge Pump Low Current of Phase Comparator
4
10
15
30
µ
A
VCC3 Supply Voltage Range
14
VCC1
–
14.4
V
VCC3 Supply Current
14
mA
All Buffers “Off”
–
0.2
0.5
One Buffer “On” when Open
–
8.0
13
One Buffer “On” at 40 mA
–
48
53
Data Format and Bus Receiver
The circuit is controlled by a 3–wire bus via Data (DA),
Clock (CL), and Enable (EN) inputs. The Data and Clock
inputs may be shared with other inputs on the IIC–Bus while
the Enable is a separate signal. The circuit is compatible with
18 and 19 bit data transmission and also has a mode for
34 bit transmission for test and additional features.
The 3–wire bus receiver receives data for the internal shift
register after the positive going edge of the EN–signal. The
data is transmitted to the band buffers on the negative going
edge of the clock pulse 4 (signal DTB1).
18 and 19 Bit Data Transmission
The programmable divider may receive 14 bit (18 bit
transmission) or 15 bit (19 bit transmission). The data is
transmitted to the programmable divider (latches A) on the
negative going edge of clock pulse 19 or on the negative
edge of the EN–signal if EN goes down after the 18th clock
pulse (signal DTF). If the programmable divider receives
14 bit, its MSB (bit N14) is internally reset. The reset pulse is
generated only if EN goes negative after the 18th clock pulse
(signal RL).
34 Bit Data Transmission
(For Test and Additional Features)
In the test mode, the programmable divider receives 15 bit
and the data is transferred to latches A on the negative edge
of clock pulse 19 (signal DTF). The information for test is
received on clock pulses 20 to 26 and transmitted to the
latches on the negative edge of pulse 34 (signal DTB2).
These latches have a power–on reset. The power–on reset
sets the programmable divider to a counting ratio of 256 or
higher and resets the corresponding latches to the test bits
T0 to T6 (signal POR). The bus receiver is not disturbed if the
data format is wrong. Useless bits are ignored. If for example
the Enable signal goes low after the clock pulse 9, bits one to
four are accepted as valid buffer information and the other
bits are ignored. If more than 34 bits are received, bit 35 and
the following are ignored.
Lock Detector
The lock–detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
MC44817/17B
4
MOTOROLA ANALOG IC DEVICE DATA
Figure 1. HF Sensitivity Test Circuit
Device is in test mode. B2, B3 are “On” and B0, B1 are “Off”.
Sensitivity is level of HF generator on 50
Ω
load (without Pin 8 loading).
16
1
2
14
HF
8
Gnd
9
B0
10
B1
11
B2
12
B3
13
Bus Controller
HF Generator
HF Out
Gnd
7
VCC1
Counter
In
ÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇÇ
VCC3
Bus
40 mA
390
Ω
390
Ω
4.7 k
4.7 k
50
Ω
50
Ω
Cable
1.0 nF
MC44817/17B
HF CHARACTERISTICS (See Figure 1)
Characteristic
Pin
Min
Typ
Max
Unit
DC Bias
8
–
1.6
–
V
Input Voltage Range
mVrms
10–80 MHz, Prescaler “Off”, T6 = 1.0
8
20
–
315
80–150 MHz
8
10
–
315
150–600 MHz
8
5.0
–
315
600–950 MHz
8
10
–
315
950–1300 MHz
8
50
–
315
–j +j
2
0.5
1
0.5
1
2
0.5
1
2
Figure 2. Typical HF Input Impedance
ZO = 50
Ω
500 MHz
1.3 GHz
1.0 GHz
50 MHz
0
MC44817/17B
5
MOTOROLA ANALOG IC DEVICE DATA
Figure 3. Pin Circuit Schematic
500
132 k
VCC1
96 k
96 k
1/2 VCC1
VCC1
96 k
96 k
1/2 VCC1
20 V
500
132 k
20 V
VCC1
96 k
96 k
1/2 VCC1
132 k
500
20 V
5.0 V
100
2.0 k
10 k
20 V
20 V
20 V
100
20 k
20 V
20 V
5.0 V
5.0 V
18 k
2.0 k
2.0 k
1.2
…
1.8 V
“On”/“Off”
“On”/“Off”
“On”/“Off”
“On”/“Off”
2.0 k
20 V
20 V
20 V
20 V
20 V
20 V
16 EN
Enable input
(3–wire bus)
15 Lock
Lock detector output
14 VCC3
Positive supply for integrated
band buffers (12 V)
13 B3
12 B2
11 B1
10 B0
9 Gnd
Circuit Ground
DA 1
Data input
(3–wire bus)
CL 2
Clock input (supplied
by a microprocessor
via 3–wire bus)
XTAL 3
Crystal oscillator
(3.2 MHz or 4.0 MHz)
Amp In 4
Negative input of
operation amplifier and
charge pump output
VTUN 5
Operational amplifier
output which provides
the tuning voltage
VCC2 6
Operational amplifier
positive supply (33 V)
VCC1 7
Positive supply of
the circuit (5.0 V)
HF In 8
HF input from
local oscillator
VCC1
100 k
Band buffer outputs
can drive up to 30 mA
(40 mA at 05 to 805C)
MC44817/17B
6
MOTOROLA ANALOG IC DEVICE DATA
Bus Timing Diagram
19
27
33
19
5
Standard Bus Protocol 18 or 19 Bit
Bus Protocol for Test and Features
Enable
B3
Buffers
Frequency
Test & Features
Random
Buffers
Frequency
Clock
Data
26
34
4
20
1
B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 T6 T5 T4 T3 T2 T1 T0 X7 X6 X5 X4 X3 X2 X1 X0
5
18
1
4
Definition of Permissible Bus Protocols
1. Bus Protocol for 18 Bit
B3 B2 B1 B0 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3
N2 N1 N0
Max Counting Ratio 16363
N14 is Reset Internally
2. Bus Protocol for 19 Bit
B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4
N3 N2 N1 N0
Max Counting Ratio 32767
– B0 to B3: Control of Band Buffers
– N0 to N14: Control of Programmable Dividers
N14 = MSB; N0 = LSB
Minimum Counting Ratio Always 17
B3 = First Shifted Bit
N0 = Last Shifted Bit
3. Bus Protocol for Test and Further Features (34 Bit)
B3 B2 B1 B0 N14
…
N0 T6 T5 T4 T3 T2 T1 T0 X7
X6
…
X1 X0
– T0 to T3: Control the Phase Comparator
– T4: Switches Test Signals to the Buffer Outputs
– T5: Division Ratio of the Reference Divider
B Version T5 = “X”
– T6: Bypasses the Prescaler (Note 1)
– X0 to X7: Are Random
B3 = First Shifted Bit
X0 = Last Shifted Bit
Definition of the Bits for Test and Features
Bit T0: Defines the Charge Pump Current of the
Bit T0:
Phase Comparator
T0 = 0
T0
= 1
Pump Current 50
µ
A Typical
Pump Current 15
µ
A Typical
Bits T1 and T2: Define the Digital Function of the Phase
Bits T1 and T2:
Comparator
T2
T1
State
Output Function of Phase Comparator
0
0
1
Normal Operation
0
1
2
High Impedance (Tri–State)
1
0
3
Upper Source “On”, Lower Source “Off”
1
1
4
Lower Source “On”, Upper Source “Off”
NOTE: 1. The phase comparator pulls high if the input frequency is too
high and it pulls low when the input frequency is too low.
(Inversion by Operational Amplifier) The phase comparator
generates a fixed duration offset pulse for each comparison
pulse (similar to the MC44802A). This guarantees operation in
the linear region. The offset pulse is a positive current pulse
(upper source).
Bit T3: Defines the Offset Pulse of the Phase
Bit T3:
Comparator
T3 = 0
T3
= 1
Offset Pulse Short (200 ns)
Normal Mode
Offset Pulse Long (350 ns)
Bit T4: Switches the Internal Frequencies Fref and
Bit T4:
FBY2 to the Buffer Outputs (B2, B3)
T4 = 0
T4
= 1
Normal Operation
Fref Switched to Buffer Output B2
FBY2 Switched to Buffer Output B3
NOTE:
Bits B2 and B3 have to be one in this case.
Fref is the reference frequency.
FBY2 is the output frequency of the programmable divider,
divided by two.
Bit T5: Defines the Division Ratio of the Reference
Bit T5:
Divider
T5 = 0
T5
= 1
Division Ratio 512
Division Ratio 1024
NOTE: The division ratio of the reference divider can only be
programmed in the 34 bit bus protocol.
In the standard bus protocol the division ratio is 512.
(The power–up reset POR sets the division ratio to 512).
On “B–version”, T5 = “X”. Division ratio 1024 fixed.
MC44817/17B
7
MOTOROLA ANALOG IC DEVICE DATA
Bit T6: Switches the Prescaler
T6 = 0
T6
= 1
Normal Operation, 1.3 GHz
Low Frequency Operation
Preamp. 2 Switched Off, 165 MHz maximum
The prescaler is bypassed and the power supply of
the prescaler is switched off. Input: 10 MHz
minimum, 20 mVrms minimum
Figure 4. Equivalent Circuit of the Integrated
Band Buffers
“On”/“Off”
ISUB
30 mA (40 mA
at 0 to 80
°
C)
VCC3 12 V
(Min VCC1, Max 14.4 V)
25 V
Protection
IB
Out
B0
…
B3
(1)
NOTE:
IB + ISUB = 8.0 mA Typical, 13 mA Max
IB = Base Current
ISUB = Substrate Current of PNP
Gnd
0.15 V Typical
0.3 V Max
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14 + 8132 x N13 +
…
+ 4 x N2 + 2 x N1 + N0
Maximum Ratio 32767
(16363 in case of 18 bit bus protocol)
Minimum Ratio 17
N0
…
N14 are the different bits for frequency information.
At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.
The Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
The Operational Amplifier
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
needs 28.5 V supply (VCC2) as minimum voltage for a
guaranteed maximum tuning voltage of 28 V.
Figure 6 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
The Oscillator
The oscillator uses a 3.2 to 4.0 MHz crystal tied to ground in
series with a capacitor. The crystal operates in the series
resonance mode.
The voltage at Pin 3 has low amplitude and low harmonic
distortion.
Figure 5. Equivalent Circuit of the Lock Output
2.0 k
25 V Protection
Lock
VCC1 5.0 V
100 k
200
µ
A Typical
1.0 nF
÷
8
Pres
Figure 6. Typical Tuner Application
11
12
13
10
B3
B2
B1 B0
12 pF
3.2/4.0 MHz
Gnd
9
6
5
4
15
B III
VHF
UHF
AGC
VTUN
33 V
Phase
Comp
Program
Divider
Lock
T6
2.7 V
Mixer
B. P. Filter
Antenna
Filter
Oscillator
IF
7
5.0 V
2
1
16
3
Osc &
Ref Div
8
Fosc
CL
DA
EN
VCC3
14 12 V
Bus
Rec
22 nF
47 k
(Note 1)
(Note 2)
330 p
47 nF
NOTES: 1. On some layouts the 100
Ω
resistor will not be required.
2. C2 = 330 pF minimum is required for stability.
External Switching
MC44817/17B
MC44817/17B
8
MOTOROLA ANALOG IC DEVICE DATA
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751B–05
(SO–16)
0.25 (0.010)
T
B
A
M
S
S
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
°
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
°
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
°
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
°
0.244
0.019
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
9
16
–A–
–B–
D
16 PL
K
C
G
–T–
SEATING
PLANE
R
X 45
°
M
J
F
P
8 PL
0.25 (0.010)
B
M
M
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Affirmative Action Employer.
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MC44817/D
*MC44817/D*
◊