¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

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¡ Semiconductor

MSM6996H/6996V/6997H/6997V/6998/6999

Single Chip CODEC

GENERAL DESCRIPTION

The MSM6996H/MSM6996V/MSM6997H/MSM6997V/MSM6998/MSM6999 are a single-channel

CODEC CMOS ICs containing filters for A/D and D/A converting of the voice signal ranging from

300 Hz to 3400 Hz.

FEATURES

• Compliance with ITU-T companding Law

MSM6996H/MSM6996V/MSM6998 :

A-law

MSM6997H/MSM6997V/MSM6999 :

m-law

• Capable of independent operation of transmission and reception

• Transmission clock in the range of 64 kHz to 2048 kHz

• Adjustable transmit gain

• 600 W drive for analog output

MSM6996H/MSM6996V/MSM6997H/MSM6997V single end drive

MSM6998/MSM6999 Push-pull drive

• Built-in analog loop back fanction

MSM6996V/MSM6997V

• Built-in reference voltage source

• Low Power Dissipation (60 mW to 70 mW Typ.)

• Package options :

16-pin plastic DIP (DIP16-P-300-2.54)

(Product name : MSM6996HRS/MSM6997HRS)

(Product name : MSM6996VRS/MSM6997VRS)

(Product name : MSM6998RS/MSM6999RS)

16-pin cer DIP (DIP16-G-300-2.54-1)

(Product name : MSM6996HAS/MSM6997HAS)

(Product name : MSM6996VAS/MSM6997VAS)

(Product name : MSM6998AS/MSM6999AS)

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name : MSM6996HGS-K/MSM6997HGS-K)

(Product name : MSM6996VGS-K/MSM6997VGS-K)

(Product name : MSM6998GS-K/MSM6999GS-K)

E2U0010-28-81

This version: Aug. 1998

Previous version: Nov. 1996

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BLOCK DIAGRAM

–

MSM6996H/V

MSM6997H/V

AIN+

AIN–

GSX

–

AOUT

XSYNC

XCLOCK

PCMOUT

RCLOCK

RSYNC

PDN/BS

PCMIN

Voltage

REF.

5th

LPF

3rd

HPF

Auto

Zero

C Ladder

SAR

Receive

Controller

Transmit

Controller

R.PWD

COMP

SAMPLE

5th

LPF

–

MSM6998, MSM6999

AIN+

AIN–

GSX

–

AOUT+

Voltage

REF.

Pre Filter

5th

LPF

3rd

HPF

Auto

Zero

SAR

COMP

SAMPLE

5th

LPF

–

AOUT–

Transmit

PLL

Receive

PLL

T.PWD

TMC

XSYNC

XCLOCK

PCMOUT

RCLOCK

RSYNC

PDN/BS

PCMIN

Receive

Controller

Transmit

Controller

R.PWD

Transmit

PLL

Receive

PLL

T.PWD

1 BS : Only MSM6997H/V

2 Only MSM6996V, MSM6997V

3 BS : Only MSM6999

Pre Filter

C Ladder

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16-Pin Plastic DIP

MSM6996HRS

MSM6997HRS

16-Pin Plastic DIP

MSM6996VRS

MSM6997VRS

16-Pin Plastic DIP

MSM6998RS

MSM6999RS

AIN+

AIN–

GSX

AOUT

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

16-Pin Cer DIP

MSM6996HAS

MSM6997HAS

16-Pin Cer DIP

MSM6996VAS

MSM6997VAS

16-Pin Cer DIP

MSM6998AS

MSM6999AS

RSYNC

AIN+

AIN–

GSX

AOUT

TMC

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

AIN+

AIN–

GSX

AOUT+

AOUT–

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

AIN+

AIN–

GSX

AOUT

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

AIN+

AIN–

GSX

AOUT

TMC

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

AIN+

AIN–

GSX

AOUT+

AOUT–

PCMIN

PCMOUT

PDN/BS

XSYNC

XCLOCK

RCLOCK

RSYNC

PIN CONFIGURATION (TOP VIEW)

NC : No connect pin

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24-Pin Plastic SOP

MSM6996HGS-K

MSM6997HGS-K

AIN+

AIN–

GSX

AOUT

PCMOUT

PDN/BS

XSYNC

RSYNC

24-Pin Plastic SOP

MSM6996VGS-K

MSM6997VGS-K

PCMIN

XCLOCK

RCLOCK

24-Pin Plastic SOP

MSM6998GS-K

MSM6999GS-K

AIN+

AIN–

GSX

AOUT

TMC

PCMOUT

PDN/BS

XSYNC

RSYNC

PCMIN

XCLOCK

RCLOCK

AIN+

AIN–

GSX

AOUT+

AOUT–

PCMOUT

PDN/BS

XSYNC

RSYNC

PCMIN

XCLOCK

RCLOCK

NC : No connect pin

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PIN AND FUNCTIONAL DESCRIPTIONS

AIN+, AIN–, GSX

These three pins are used for the transmit level adjustment.

AIN+ is a non-inverting analog input pin which is connected to the non-inverting input of a transmit

amplifier.

AIN– is an inverting analog input pin which is connected to the inverting input of the transmit

amplifier.

GSX is a transmit amplifier output pin.

Adjustment can be done by following method.

–

AIN–

Gain = 1 +

AIN+

GSX

Active

Filter

Analog

Input

< 10

Notes: 1. R

+ R

> 10 kW

2. When the DC off-set voltage of analog input is more than 20 mV, C1 and R1 should

provide for DC blocking.

In this case, cut-off frequency of HPF, composed by R

and C

, should be less than 30 Hz.

3. R

should be less than 20 kW

AG is an analog ground.

AG is connected to the analog system ground.

AOUT

AOUT is the analog signal output pin for the MSM6996H/V and MSM6997H/V.

The output voltage range is 5 V

. This output can drive the 600 W resistor.

AOUT+, AOUT–

Analog output for the MSM6998 and MSM6999.

The output signal amplitudes are 5 V

. The AOUT– output is inverted to the AOUT+ output. These

outputs can drive a 600 W impedance.

is the positive power supply.

The voltage supplied to this pin should be +5 V

5%.

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PCMIN

PCM signal input.

The serial input PCM signal is converted from digital to analog, synchronizing with the synchronous

signal RSYNC and clock signal RCLOCK.

The data rate of PCM signal ranges from 64 kbps to 2048 kbps.

The PCM signal is read at the falling edge of the clock signal and latched into the internal register

when finished to read eight bits data.

The top of the PCM data is specified by RSYNC pulse timing.

RCLOCK

Receive clock pulse input.

The frequency of this clock pulse should be identified with the data rate of PCM input signal at the

PCMIN pin.

This RCLOCK signal can be a continuous clock or a burst clock with nine bits or more.

In the case of a burst clock, input the following timing.

XCLOCK

Transmit clock input.

The PCM output data rate from the PCMOUT pin is set by this clock frequency.

The applicable clock frequencies range from 64 kHz to 2048 kHz.

This XCLOCK signal can be a continuous clock or a burst clock with nine bits or more.

In the case of a burst clock, input the following timing.

MSD

PCMOUT

XCLOCK

XSYNC

9 Clocks are required

MSD

PCMIN

RCLOCK

RSYNC

9 Clocks are required

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RSYNC

Receive synchronizing signal input.

Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive

synchronizing signal.

The whole timing signal in the receive section are synchronize by this synchronizing signal.

This signal must be synchronize in phase with RCLOCK.

The frequency should be 8 kHz

50 ppm to guarantee the AC characteristics of receive section.

However, same as the RCLOCK frequency, this device can operate in the range of 8 kHz

2 kHz, with

no guarantee of adherence to the electrical characteristics in this specification as a catalogue value.

Fixing this signal to logic "1" or "0", the receive circuit is driver in a power down state.

XSYNC

Transmit synchronizing signal input.

The PCM output signal from the PCMOUT pin is output in synchronization with this transmit

synchronizing signal.

All transmit timing signals are triggered to synchronize with this signal. This signal should be

synchronized in phase with XCLOCK pulse.

The frequency should be 8 kHz

50 ppm to guarantee the AC characteristics of transmit section.

Fixing this signal to logic "1" or "0", the transmit circuit is driver in a power down state.

Ground of digital signal.

This pin is electrically separated from the AG pin in this device.

The DG pin must be connected to the AG pin on the printed circuit board to make common to the

AG pin.

PDN/BS

Power down signal input.

When this input is held at low level more than 1 ms, the device is put into the power-down mode.

PCMOUT

PCM signal output.

The PCM output signal is output in synchronization with the rising edge of XCLOCK pulse orderly

from MSD first. (The first bit of the PCM signal may output at the rising edge of XSYNC pulse,

according to the timing of XSYNC and XCLOCK pulse.). During the PCMOUT signal output except

the 8-bit pulses, the pin is in an open state, therefore, multiple connections by wired-OR are easily

possible at this pin.

The code companding law and output code format depend on ITU-T Recommendation G.711, and

for the MSM6996H, MSM6996V, and MSM6998 (A-law) the output PCM signals are obtained by

inverting the even bits of signals.

Input/Output

Level

+Full scale

–0

–Full scale

PCMIN/PCMOUT

MSM6996 (A-law)

MSM6997 (

m-law)

MSM6998 (A-law)

MSM6999 (

m-law)

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ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

* : The value for the MSM6997 and MSM6999

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Storage Temperature

Symbol

AIN

DIN

STG

Rating

0 to 7

–0.3 to V

+ 0.3

–0.3 to V

+ 0.3

–55 to +150

Unit

°C

–7 to 0

Condition

—

(Ta = 0°C to 70°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power Supply Voltage

Analog Input Voltage

AIN

Input High Voltage

Input Low Voltage

—

Connect AIN– and GSX

XSYNC, XCLOCK, PCMIN,

RSYNC, RCLOCK, TMC, PDN/BS

4.75

5.25

–5.25

–5

–4.75

—

P-P

2.0

—

0.8

Clock Frequency

XCLOCK, RCLOCK

kHz

—

Sync Pulse Frequency

XSYNC, RSYNC

—

kHz

Clock Duty Ratio

XCLOCK, RCLOCK

Digital Input Rise Time

—

Digital Input Fall Time

—

XSYNC, XCLOCK, PCMIN,

RSYNC, RCLOCK (Fig. 1)

Transmit Sync Timing

—

100

—

XCLOCKÆXSYNC (Fig. 2)

XSYNCÆXCLOCK (Fig. 2)

Receive Sync Timing

—

100

—

RCLOCKÆRSYNC (Fig. 2)

RSYNCÆRCLOCK (Fig. 2)

1/fc

—

1/fc

—

Transmit Sync Pulse Width

Receive Sync Pulse Width

100

—

100

—

PCMIN Set-up Time

PCMIN Hold Time

200

—

BS Set-up Time *

200

—

BS Hold Time *

600

—

Analog Output Load

—

100

—

Digital Output Load

—

100

AOUT, AOUT+, AOUT–

—

–200

—

+200

Allowable Analog Input

Offset Voltage

Transmit gain stage, Gain = 1

2048

–20

—

+20

Transmit gain stage, Gain = 10

—

GSK

—

Operating Temperature

°C

—

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ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

* : The upper is specified for the MSM6996/MSM6997 and the lower for the MSM6998/MSM6999

= +5 V ±5%, V

= –5 V ±5%, Ta = 0°C to 70˚C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power Supply Current

(Stand-by)

DD1

SS1

DD2

SS2

Input High Voltage

XCLOCK, RCLOCK

2048 kHz

—

7.0

—

6.5

—

3.0

—

1.5

2.2

—

Input Low Voltage

—

< 0.5

2.0

Input Leakage Current

—

< 0.2

0.5

Output Leakage Current

—

< 5

Analog Output Offset Voltage

OFF

–150

+150

—

Input Capacitance

—

< 3.4 kHz

Analog Input Resistance

(Operating)

—

0.8

—

0.1

0.4

Output Low Voltage