¡ Semiconductor
MSM54V16272
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¡ Semiconductor
MSM54V16272
262,144-Word
¥ 16-Bit Multiport DRAM
DESCRIPTION
The MSM54V16272 is a 4-Mbit CMOS multiport DRAM composed of a 262,144-word by 16-bit
dynamic RAM, and a 512-word by 16-bit SAM. Its RAM and SAM operate independently and
asynchronously.
It supports three types of operations: random access to RAM port, high speed serial access to
SAM port, and bidirectional transfer of data between any selected row in the RAM port and the
SAM port. In addition to the conventional multiport DRAM operating modes, the MSM54V16272
features block write and flash write functions on the RAM port, and a split data transfer
capability on the SAM port. The SAM port requires no refresh operation because it uses static
CMOS flip-flops.
FEATURES
• Single power supply: 3.3 V
±
0.3 V
• Full TTL compatibility
• Multiport organization
RAM : 256K word ¥ 16 bits
SAM : 512 word ¥ 16 bits
• Fast page mode
• Write per bit
• Byte read/write
• Masked flash write
• Masked block write (8 columns)
• Package options:
64-pin 525 mil plastic SSOP
(SSOP64-P-525-0.80-K)
(Product : MSM54V16272-xxGS-K)
70/64-pin 400 mil plastic TSOP (Type II)(TSOPII70/64-P-400-0.65-K)(Product : MSM54V16272-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
• RAS only refresh
• CAS before RAS refresh
• CAS before RAS self-refresh
• Hidden refresh
• Serial read/write
• 512 tap location
• Bidirectional data transfer
• Split transfer
• Masked write transfer
• Refresh: 512 cycles/8 ms
Access Time
Cycle Time
Power Dissipation
RAM
RAM
Operating
Standby
SAM
SAM
60 ns
120 ns
160 mA
8 mA
18 ns
22 ns
70 ns
140 ns
150 mA
8 mA
20 ns
22 ns
Family
MSM54V16272-60
MSM54V16272-70
E2L0024-17-Y1
This version: Jan. 1998
Previous version: Dec. 1996
¡ Semiconductor
MSM54V16272
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PIN CONFIGURATION (TOP VIEW)
Note:
The same power supply voltage must be provided to every V
CC
pin, and the same GND
voltage level must be provided to every V
SS
pin.
Pin Name
Function
A0 - A8
Address Input
RAS
Row Address Strobe
CASL
Column Address Strobe Lower
TRG
Transfer/Output Enable
CASU
Column Address Strobe Upper
Pin Name
Function
SC
Serial Clock
SE
SAM Port Enable
DSF
Special Function Input
V
CC
Power Supply (3.3 V)
NC
No Connection
DQ0 - DQ15
RAM Inputs/Outputs
SDQ0 - SDQ15
SAM Inputs/Outputs
QSF
Special Function Output
V
SS
Ground (0 V)
WE
Write Enable
64-Pin Plastic SSOP
70/64-Pin Plastic TSOP (
II)
(K Type)
DQ15
SDQ15
DQ14
SDQ14
V
CC
DQ13
SDQ13
DQ12
SDQ12
V
SS
DQ11
SDQ11
DQ10
SDQ10
V
CC
DQ9
SDQ9
SDQ7
DQ7
SDQ6
DQ6
V
SS
SDQ5
DQ5
SDQ4
DQ4
V
SS
SDQ0
DQ0
SDQ1
DQ1
V
CC
SDQ2
DQ2
V
CC
SC
V
SS
V
CC
SDQ3
DQ3
V
SS
SE
TRG
A5
A4
V
CC
DQ8
V
SS
DSF
NC
CASU
QSF
A0
A1
A2
A3
V
SS
SDQ8
CASL
WE
A6
A7
A8
RAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DQ15
SDQ15
DQ14
SDQ14
V
CC
DQ13
SDQ13
DQ12
SDQ12
V
SS
DQ11
SDQ11
DQ10
SDQ10
V
CC
DQ9
SDQ9
SDQ7
DQ7
SDQ6
DQ6
V
SS
SDQ5
DQ5
SDQ4
DQ4
V
SS
SDQ0
DQ0
SDQ1
DQ1
V
CC
SDQ2
DQ2
V
CC
SC
V
SS
V
CC
SDQ3
DQ3
V
SS
SE
TRG
A5
A4
V
CC
DQ8
V
SS
DSF
NC
CASU
QSF
A0
A1
A2
A3
V
SS
SDQ8
CASL
WE
A6
A7
A8
RAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
¡ Semiconductor
MSM54V16272
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BLOCK DIAGRAM
Column
Address
Buffer
Row
Address
Buffer
Refresh
Counter
A0 - A8
SAM
Address
Buffer
SAM Address
Counter
SAM Stop
Control
Row Decoder
Column Decoder
Sense Amp.
512 ¥ 512 ¥ 16
RAM ARRAY
Gate
SAM
Gate
SAM
SDQ 0 - 15
QSF
Serial Decoder
Block Write
Control
I/O Control
Flash Write
Control
SAM Input
Buffer
SAM Output
Buffer
Column Mask
Register
Color Register
Mask Register
RAM Input
Buffer
RAM Output
Buffer
Timing
Generator
RAS
CASU / CASL
TRG
WE
DSF
SC
SE
V
CC
V
SS
DQ 0 - 15
SE
¡ Semiconductor
MSM54V16272
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Input Output Voltage
V
T
–0.5 to 4.6
V
Output Current
I
OS
50
mA
Power Dissipation
P
D
1
W
Operating Temperature
T
opr
0 to 70
°C
Storage Temperature
T
stg
–55 to 150
°C
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
—
—
(Note: 1)
Recommended Operating Conditions
Parameter
Symbol
Unit
Power Supply Voltage
V
CC
V
Input High Voltage
V
IH
V
Input Low Voltage
V
IL
V
Min.
3.0
2.0
–0.3
Typ.
3.3
—
—
Max.
3.6
V
CC
+ 0.3
0.8
(Ta = 0°C to 70°C) (Note: 2)
Capacitance
Parameter
Symbol
Min.
Unit
Input Capacitance
C
i
—
pF
Input/Output Capacitance
C
io
—
pF
Max.
6
7
Output Capacitance
C
o
(QSF)
—
pF
7
(V
CC
= 3.3 V ±0.3 V, f = 1 MHz, Ta = 25°C)
Note:
This parameter is periodically sampled and is not 100% tested.
DC Characteristics 1
Parameter
Symbol
Condition
Output "H" Level Voltage
V
OH
I
OH
= –2 mA
Output "L" Level Voltage
V
OL
I
OL
= 2 mA
Input Leakage Current
I
LI
0 £ V
IN
£ V
CC
All other pins not
under test = 0 V
Min.
2.4
—
–10
Max.
—
0.4
10
Unit
V
mA
Output Leakage Current
I
LO
0 £ V
OUT
£ V
CC
Output Disable
–10
10
¡ Semiconductor
MSM54V16272
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DC Characteristics 2
-60
-70
Unit Note
Symbol
Item (RAM)
SAM
Max.
Max.
Operating Current
Standby
(RAS, CAS Cycling, t
RC
= t
RC
min.)
Active
Standby Current
(RAS, CAS = V
IH
)
RAS Only Refresh Current
(RAS Cycling, CAS = V
IH
, t
RC
= t
RC
min.)
Page Mode Current
(RAS = V
IL
, CAS Cycling, t
PC
= t
PC
min.)
CAS before RAS Refresh Current
(RAS Cycling, CAS before RAS, t
RC
= t
RC
min.)
Data Transfer Current
(RAS, CAS Cycling, t
RC
= t
RC
min.)
Flash Write Current
(RAS, CAS Cycling, t
RC
= t
RC
min.)
Block Write Current
(RAS, CAS Cycling, t
RC
= t
RC
min.)
Standby
Active
Standby
Active
Standby
Active
Standby
Active
Standby
Active
Standby
Active
Standby
Active
(V
CC
= 3.3 V ±0.3 V, Ta = 0°C to 70°C)
120
110
mA
3, 4
I
CC1
160
150
17
8
8
55
55
3, 4
120
110
3, 4
160
150
17
120
110
3, 4
160
150
18
100
90
3, 4
140
130
3, 4
110
100
3, 4
150
140
17
110
100
3, 4
150
140
3, 4
110
100
3, 4
150
140
3, 4
I
CC1
A
I
CC2
I
CC2
A
I
CC3
I
CC3
A
I
CC4
I
CC4
A
I
CC5
I
CC5
A
I
CC6
I
CC6
A
I
CC7
I
CC7
A
I
CC8
I
CC8
A
CAS before RAS Self-Refresh Current
(RAS, CAS £ 0.2 V)
Standby
1
1
3, 4
I
CC9
¡ Semiconductor
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AC Characteristics (1/3)
Parameter
Symbol
Note
Unit
t
RC
t
PRWC
t
AA
t
CAC
t
CPA
t
RASP
t
CAS
t
RCD
-70
-60
t
PC
t
RAC
t
OFF
t
RSH
t
CSH
t
T
t
RP
t
RAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
AR
t
RCS
t
RCH
t
RRH
t
WCS
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
RWC
t
RAL
t
CRP
t
CP
Access Time from Column Address
Column Address Hold Time referenced to RAS
Column Address Set-up Time
Row Address Set-up Time
Access Time from CAS
Column Address Hold Time
CAS Pulse Width
CAS Precharge Time (Fast Page Mode)
Access Time from CAS Precharge
CAS to RAS Precharge Time
CAS Hold Time
Write Command to CAS Lead Time
Output Buffer Turn-off Delay
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write Cycle Time
Row Address Hold Time
RAS Pulse Width (Fast Page Mode Only)
Random Read or Write Cycle Time
RAS to CAS Delay Time
Read Command Hold Time
Read Command Set-up Time
Read Modify Write Cycle
RAS Precharge Time
Read Command Hold Time referenced to RAS
Write Command to RAS Lead Time
Access Time from RAS
RAS to Column Address Delay Time
Column Address to RAS Lead Time
RAS Pulse Width
RAS Hold Time
Transition Time (Rise and Fall)
Write Command Hold Time referenced to RAS
Write Command Set-up Time
Write Command Pulse Width
Write Command Hold Time
ns
ns
ns
ns
ns
ns
ns
ns
14
ns
ns
10
ns
ns
ns
ns
ns
14
11
11
8, 14
8, 15
8, 15
8, 14
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
124
—
—
—
2
70
81
15
15
35
—
0
50
20
55
70
12
0
10
0
10
55
0
0
0
0
10
55
10
15
15
170
35
10
10
Min.
104
—
—
—
2
60
76
15
15
30
—
0
40
15
45
60
12
0
10
0
10
50
0
0
0
0
10
50
10
15
15
140
30
5
10
ns
ns
13
Max.
—
35
20
40
35
100k
—
10k
—
70
17
—
—
—
10k
50
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
30
15
35
35
100k
—
10k
—
60
15
—
—
—
10k
42
30
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
¡ Semiconductor
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AC Characteristics (2/3)
Parameter
Symbol
Note
Unit
t
DS
t
RWD
t
CWD
t
DZC
t
DZO
t
CSR
t
REF
t
WSR
-70
-60
t
DHR
t
AWD
t
OEA
t
CHR
t
RPC
t
OEZ
t
OEH
t
ROH
t
RWH
t
FSC
t
CFH
t
MS
t
MH
t
THS
t
THH
t
TLS
t
TLH
t
DH
t
RTH
t
ATH
t
CTH
t
FSR
t
RFH
t
FHR
Column Address to WE Delay Time
CAS Hold Time for CAS before RAS Cycle
CAS Set-up Time for CAS before RAS Cycle
CAS to WE Delay Time
Data Hold Time
Data Hold Time referenced to RAS
Data Set-up Time
Data to CAS Delay Time
Data to TRG Delay Time
DSF Set-up Time referenced to RAS
Write Per Bit Mask Data Hold Time
Write Per Bit Mask Data Set-up Time
TRG Command Hold Time
Refresh Period
DSF Hold Time referenced to RAS (1)
RAS Hold Time referenced to TRG
RAS Precharge to CAS Active Time
RAS to WE Delay Time
WE Hold Time
Access Time from TRG
WE Set-up Time
Output Buffer Turn-off Delay from TRG
DSF Hold Time referenced to RAS (2)
DSF Hold Time referenced to CAS
TRG Low Hold Time referenced to Column Address
TRG Low Hold Time referenced to CAS
DSF Set-up Time referenced to CAS
TRG High Hold Time
TRG High Set-up Time
TRG Low Hold Time
TRG Low Set-up Time
TRG Low Hold Time referenced to RAS
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
13
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
13
Min.
0
40
0
0
0
5
90
0
55
55
10
10
0
15
10
0
10
0
10
0
10
0
10
12
60
25
20
0
10
55
—
—
Min.
0
35