¡ Semiconductor

MSM51V17405D/DSL

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DESCRIPTION

The MSM51V17405D/DSL is a 4,194,304-word ¥ 4-bit dynamic RAM fabricated in Oki's silicon-gate

CMOS technology. The MSM51V17405D/DSL achieves high integration, high-speed operation,

and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/

double-layer metal CMOS process. The MSM51V17405D/DSL is available in a 26/24-pin plastic SOJ

or 26/24-pin plastic TSOP. The MSM51V17405DSL (the self-refresh version) is specially designed

for lower-power applications.

FEATURES

• 4,194,304-word ¥ 4-bit configuration

• Single 3.3 V power supply,

0.3 V tolerance

• Input

: LVTTL compatible, low input capacitance

• Output : LVTTL compatible, 3-state

• Refresh : 2048 cycles/32 ms, 2048 cycles/128 ms (SL version)

• Fast page mode with EDO, read modify write capability

• CAS before RAS refresh, hidden refresh, RAS-only refresh capability

• CAS before RAS self-refresh capability (SL version)

• Multi-bit test mode capability

• Package options:

26/24-pin 300 mil plastic SOJ

(SOJ26/24-P-300-1.27)

(Product : MSM51V17405D/DSL-xxSJ)

26/24-pin 300 mil plastic TSOP

(TSOPII26/24-P-300-1.27-K) (Product : MSM51V17405D/DSL-xxTS-K)

xx indicates speed rank.

PRODUCT FAMILY

¡ Semiconductor

MSM51V17405D/DSL

4,194,304-Word

¥ 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO

MSM51V17405D/DSL-70 70 ns

124 ns

84 ns

288 mW

360 mW

Family

Access Time (Max.)

Cycle Time

(Min.)

Standby (Max.)

Power Dissipation

MSM51V17405D/DSL-50

RAC

50 ns

35 ns

25 ns

20 ns

CAC

13 ns

20 ns

OEA

13 ns

MSM51V17405D/DSL-60 60 ns

104 ns

324 mW

30 ns

15 ns

Operating (Max.)

1.8 mW/

0.72 mW (SL version)

Preliminary

E2G0125-17-61

This version: Mar. 1998

¡ Semiconductor

MSM51V17405D/DSL

2/17

PIN CONFIGURATION (TOP VIEW)

Note :

The same power supply voltage must be provided to every V

pin, and the same GND

voltage level must be provided to every V

pin.

26/24-Pin Plastic SOJ

26/24-Pin Plastic TSOP

(K Type)

DQ2

DQ3

DQ1

25 DQ4

26 V

21 A9

A10

19 A8

DQ2

DQ1

A10

DQ3

DQ4

Pin Name

Function

A0 - A10

Address Input

RAS

Row Address Strobe

CAS

Column Address Strobe

DQ1 - DQ4

Data Input/Data Output

Output Enable

Write Enable

Power Supply (3.3 V)

Ground (0 V)

CAS

RAS

No Connection

¡ Semiconductor

MSM51V17405D/DSL

4/17

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Recommended Operating Conditions

Capacitance

*: Ta = 25

Voltage on Any Pin Relative to V

Short Circuit Output Current

Power Dissipation

Operating Temperature

Storage Temperature

Symbol

opr

stg

–0.5 to 4.6

0 to 70

–55 to 150

Rating

°C

Parameter

Unit

Power Supply Voltage

Input High Voltage

Input Low Voltage

Symbol

3.3

—

Typ.

Parameter

3.0

2.0

–0.3

Min.

3.6

+ 0.3

0.8

Max.

(Ta = 0°C to 70°C)

Unit

Input Capacitance (A0 - A10)

Input Capacitance (

RAS, CAS, WE, OE)

Output Capacitance (DQ1 - DQ4)

IN1

Symbol

IN2

I/O

Max.

Unit

Parameter

= 3.3 V ±0.3 V, Ta = 25°C, f = 1 MHz)

—

Typ.

¡ Semiconductor

MSM51V17405D/DSL

5/17

DC Characteristics

Parameter

Symbol

Condition

MSM51V17405

D/DSL-50

MSM51V17405

D/DSL-60

MSM51V17405

D/DSL-70

= 3.3 V ±0.3 V, Ta = 0°C to 70°C)

= –2.0 mA

Output High Voltage

= 2.0 mA

Output Low Voltage

0 V £ V

£ V

+ 0.3 V;

All other pins not

Input Leakage Current

under test = 0 V

DQ disable

Output Leakage Current

0 V £ V

£ V

RAS, CAS cycling,

Average Power

= Min.

Supply Current

(Operating)

RAS, CAS = V

Power Supply

RAS, CAS

Current (Standby)

RAS cycling,

Average Power

CAS = V

Supply Current

= Min.

(

RAS-only Refresh)

RAS = V

Power Supply

CAS = V

Current (Standby)

DQ = enable

Average Power

CAS before RAS

Supply Current

(

CAS before RAS Refresh)

Average Power

RAS £ 0.2 V,

Supply Current

CAS £ 0.2 V

(

CAS before RAS

CC1

CC2

CC3

CC5

CC6

CCS

≥ V

–0.2 V

Min.

Max.

Min.

Max.

Min.

Max.

Unit Note

RAS cycling,

2.4

–10

—

0.4

100

0.5

100

300

2.4

–10

—

0.4

0.5

300

2.4

–10

—

0.4

0.5

300

—

200

—

200

—

200

1, 2

1, 5

= 62.5 ms,

Average Power

CAS before RAS,

Supply Current

RAS

£ 1 ms

(Battery Backup)

CC10

—

300

—

300

—

300

1, 4,

RAS = V

Average Power

CAS cycling,

Supply Current

HPC

= Min.

(Fast Page Mode)

CC7

—

100

—

1, 3

Self-Refresh)

Notes : 1. I

Max. is specified as I

for output open condition.

2. The address can be changed once or less while RAS = V

3. The address can be changed once or less while CAS = V

4. V

– 0.2 V £ V

£ V

+ 0.3 V, –0.3 V £ V

£ 0.2 V.

5. SL version.

¡ Semiconductor

MSM51V17405D/DSL

6/17

AC Characteristics (1/2)

Parameter

MSM51V17405

D/DSL-60

MSM51V17405

D/DSL-70

MSM51V17405

D/DSL-50

= 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13

Random Read or Write Cycle Time

Read Modify Write Cycle Time

Fast Page Mode Cycle Time

Fast Page Mode Read Modify Write

Cycle Time

Access Time from

RAS

Access Time from

CAS

Access Time from Column Address

Access Time from

CAS Precharge

CAS to Data Output Buffer Turn-off Delay Time

Transition Time

RAS Precharge Time

RAS Pulse Width

RAS Pulse Width (Fast Page Mode with EDO)

RAS Hold Time

CAS Pulse Width

CAS Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

CAS to RAS Precharge Time

Row Address Set-up Time

Row Address Hold Time

Column Address Set-up Time

Column Address Hold Time

Column Address to

RAS Lead Time

Access Time from

OE to Data Output Buffer Turn-off Delay Time

Refresh Period

RAS Hold Time referenced to OE

Unit

Min.

Max.

Min.

Max.

RAS Hold Time from CAS Precharge

Symbol

RWC

HPC

HPRWC

RAC

CAC

CPA

CEZ

RAS

RASP

RSH

CAS

CSH

RCD

RAD

CRP

ASR

RAH

ASC

CAH

RAL

OEA

OEZ

REF

ROH

RHCP

Note

Min.

Max.

Output Low Impedance Time from

CAS

CLZ

CAS Precharge Time (Fast Page Mode with EDO) t

4, 5, 6

4, 5

4, 6

7, 8

110

—

10,000

100,000

—

10,000

—

124

160

—

10,000

100,000

—

10,000

—

104

135

—

10,000

100,000

—

10,000

—

Refresh Period (SL version)

REF

—

128

—

128

—

128

Data Output Hold After

CAS Low

WE to Data Output Buffer Turn-off Delay Time

RAS to Data Output Buffer Turn-off Delay Time

DOH

WEZ

REZ

7, 8

—

OE Hold Time from CAS (DQ Disable)

CHO

—

¡ Semiconductor

MSM51V17405D/DSL

7/17

AC Characteristics (2/2)

MSM51V17405

D/DSL-60

MSM51V17405

D/DSL-70

MSM51V17405

D/DSL-50

Write Command Pulse Width

Write Command to

CAS Lead Time

Write Command to

RAS Lead Time

Data-in Set-up Time

CAS to WE Delay Time

RAS to WE Delay Time

Column Address to

WE Delay Time

RAS to CAS Hold Time (CAS before RAS)

CAS Active Delay Time from RAS Precharge

Data-in Hold Time

Write Command Hold Time

OE Command Hold Time

OE to Data-in Delay Time

= 3.3 V ±0.3 V, Ta = 0°C to 70°C) Note 1, 2, 3, 12, 13

Write Command Set-up Time

CWL

RWL

CWD

RWD

AWD

CHR

RPC

WCH

OEH

OED

WCS

Min.

Max.

Parameter

Symbol

Unit Note

Min.

Max.

Min.

Max.

RAS to CAS Set-up Time (CAS before RAS) t

CSR

WE to RAS Precharge Time (CAS before RAS) t

WRP

WE Hold Time from RAS (CAS before RAS) t

WRH

RAS to WE Set-up Time (Test Mode)

WTS

CAS Precharge WE Delay Time

CPWD

RAS to WE Hold Time (Test Mode)

WTH

—

RAS Pulse Width

RASS

100

—

100

—

100

—

(

CAS before RAS