MSM13_14Q_35 mDS

Oki Semiconductor

MSM13Q0000/14Q0000

0.35 µm Sea of Gates Arrays

DESCRIPTION

Oki’s 0.3 5 µm ASIC products deliver ultra-high performance and high density at low power dissipation.

The MSM13Q0000/14Q0000 series devices (referred to as “MSM13Q/14Q”) are implemented with the

industry-standard Cell-Based Array (CBA) architecture in a Sea-of-Gates (SOG) structure. Built in a

0.35 µm drawn CMOS technology (with an L-Effective of 0.27 µm), these SOG devices are available in

three layers (MSM13Q) and four layers (MSM14Q) of metal. The semiconductor process is adapted from

Oki’s production-proven 64-Mbit DRAM manufacturing process.

The MSM13Q/14Q Series contains 6 arrays each, offering over 1 million raw gates and 352 I/O pads. Up

to 66% and 90% of the raw gates can be used for the 3-layer and 4-layer arrays, respectively. Oki’s 0.35

µm family is optimized for 3-V core operation with optimized 3-V I/O buffers and 5-V tolerant 3-V buff-

ers. These SOG products are designed to fit the most popular plastic quad flat packs (QFPs), thin QFPs

(TQFPs) , and plastic ball grid array (PBGA) packages.

The MSM13Q/14Q Series uses the popular CBA architecture from Silicon Architects of Synopsys which

mixes two types of cells (8-transistor compute cells and 4-transistor drive cells) on the same die to deliver

high gate density and high drives. The CBA is supported by a rich macro library, optimized for synthesis.

Memory blocks are efficiently created by Oki’s memory compilers to generate single- and dual-port

RAM’s in high-density and low-power configurations with synchronous RAM options.

As such, the MSM13Q/14Q series is well suited to memory-intensive designs with high production vol-

umes approaching the real estate and cost savings of standard cells. At the same time, its SOG architec-

ture allows rapid prototyping turnaround times. Thus, Oki’s MSM13Q/14Q family offers the best of two

worlds: quick prototyping of a gate array and low production cost of a standard cell.

Oki’s 0.35 µm ASIC products are supported by leading-edge CAD tools including a synthesis-linked

floorplanner, motive static timing analyzer, and H-clock tree methodology. They are further supported

by specialized macrocells including phase-locked loop (PLL), pseudo-emitter coupled logic (PECL),

peripheral component interconnect (PCI), universal synchronous receiver/transmitter (UART) cells, and

ARM7TDMI RISC cores.

FEATURES

• 0.35 µm drawn 3- and 4-layer metal CMOS

• Optimized 3.3-V core

• Optimized 3-V I/O and 3-V I/O that is 5-V

tolerant

• CBA SOG architecture

• Over 1.0M raw gates and 352 pads

• User-configurable I/O with V

, V

, TTL, 3-

state, and 1- to 24-mA options

• Slew-rate-controlled outputs for low-radiated

noise

• H-clock tree cells which reduce the maximum

skew for clock signals

• User-configurable single and dual-port;

synchronous or asynchronous memories

• Specialized macrocells including PLL, PECL,

PCI, UART, and ARM7TDMI

• Floorplanning for front-end simulation, back-

end layout controls, and link to synthesis

• Joint Test Action Group (JTAG) boundary scan

and scan-path ATPG

• Support for popular CAE systems, including

Cadence, IKOS, Mentor Graphics, Synopsys,

Viewlogic, and Zycad

MSM13Q0000/14Q0000

––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

Oki Semiconductor

ARRAY ARCHITECTURE

The primary components of a 0.35 µm MSM13Q/14Q circuit include:

• I/O base cells

• Configurable I/O pads for V

, V

, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant)

• V

and V

pads dedicated to wafer probing

• Separate power bus for output buffers

• Separate power bus for internal core logic and input buffers

• Core base modules containing three compute cells for each drive cell

• Isolated gate structure for reduced input capacitance and increased routing flexibility

Each array has 24 dedicated corner pads for power and ground use during wafer probing, with 4 pads

per corner. The arrays also have separate power rings for the internal core functions (V

DDC

and V

SSC

)

and output drive transistors (V

DDO

and V

SSO

The array architecture uses optimally sized transistors to efficiently implement logic and memory in a

metal programmable technology. CBA uses two types of cells: compute cells and drive cells. The com-

pute cell employs four PMOS and four NMOS trasnsistors whose sizes are optimized for logic and mem-

ory implementations as shown in

Figure 1

. The quantity and size of the transistors in a compute cell are

carefully selected to maximize the efficiency of most commonly used functions in VLSI design. The drive

cell consists of two large PMOS pull-up transistors and two large pull-down transistors. The compute

and drive cells are tiled to create a channelless core array, with three comput cells for each drive cell as

shown in

Figure 2

. The 3:1 ratio of compute to drive cells was selected for optimal implementation of

emerging applications. Macrocells are created using either compute cells, drive cells, or combinations of

compute and drive cells.

MSM13Q/14Q FAMILY LISTING

MSM13Q/14Q

Series

PAD No.

Raw Gate

(Gates)

Usable Gate

M13Q(3LM)

Usable Gate

M14Q(4LM)

Raw Gate

Row

Column

0150

144

157,192

105,319

143,045

196

802

0230

176

242,400

152,712

208,464

240

1,010

0340

208

346,176

204,244

276,941

288

1,202

0530

256

536,400

289,656

391,572

360

1,490

0840

320

847,048

415,054

567,522

452

1,874

1020

352

1,033,000

475,180

650,790

500

2,066

MSM13Q0000/14Q0000

Oki Semiconductor

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (V

= 0 V, T

= 25°C)

[1]

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions

in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameter

Symbol

Conditions

Rated Value

Unit

Power supply voltage

-0.3 to +4.6

Input voltage

Normal buffers

-0.3 to V

+0.3

5-V tolerant

-0.3 to 6.0

Output voltage

Normal buffers

-0.3 to V

+0.3

5-V tolerant

-0.3 to 6.0

Input current

Normal buffers

-10 to +10

5-V tolerant

-6 to +6

Output current per I/O

Normal buffers

= 1, 2, 4, 6, 8, 12, 24 mA

-24 to +24

5-V tolerant

= 2, 4, 6, 8, 12 mA

-8 to +8

Storage temperature

stg

–

-65 to +150

°C

Recommended Operating Conditions (V

= 0 V)

Parameter

Symbol

Rated Value

Unit

Power supply voltage

(3 V)

+3.0 to +3.6

Junction temperature

-40 to +85

°C

–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

MSM13Q0000/14Q0000

Oki Semiconductor

DC Characteristics (V

= 3.0 to 3.6 V, V

= 0 V, T

= -40°C to +85°C)

Parameter

Symbol

Conditions

Rated Value

[1]

JEDEC Compatible; JESD8-1A LVTTL.

Unit

Min.

Typ

[2]

Typical condition is

= 3.3 V and T

= 25

on a typical process.

Max.

High-level input voltage

Normal buffer

2.0

–

+ 0.3

5-V tolerant

2.0

–

5.5

Low-level input voltage

Normal buffer

TTL input

-0.3

–

0.8

5-V tolerant

TTL input

-0.3

–

0.8

TTL- level Schmitt trigger input

threshold voltage

Normal buffer

TTL input

–

1.5

2.0

0.7

1.0

–

∆

- V

0.4

0.5

–

5-V tolerant

TTL 5-V tolerant input

–

1.5

2.0

0.7

1.0

–

∆

- V

0.4

0.5

–

High-level output voltage

Normal buffer

= -100 µA

- 0.2

–

= -1, -2, -4, -6, -8, -12, -24 mA

2.4

–

5-V tolerant

= -100 µA

- 0.2

–

= -1, -2, -4, -6, -8, -12 mA

2.4

–

Low-level output voltage

Normal buffer

= 100 µA

–

0.2

= 1, 2, 4, 6, 8, 12, 24mA

–

0.4

5-V tolerant

= 100 µA

–

0.2

= 1, 2, 4, 6, 8, 12 mA

–

0.4

High-level input current

Normal buffer

= V

–

0.1

µA

= V

(50-k

Ω

pull-down)

200

5-V tolerant

= V

–

0.1

= V

(50-k

Ω

pull-down)

200

Low-level input current

Normal buffer

= V

-10

-0.1

= V

(50-k

Ω

pull-up)

-200

-66

-10

= V

(3-k

Ω

pull-up)

-3.3

-1.1

-0.3

5-V tolerant

= V

-10

-0.1

–

µA

3-state output leakage current

Normal buffer

OZH

= V

–

0.1

µA

= V

(50-k

Ω

pull-down)

-66

200

OZL

= V

-10

-0.1

–

= V

(50-k

Ω

pull-up)

-200

-66

-10

= V

(3-k

Ω

pull-up)

-3.3

-1.1

-0.3

5-V tolerant

OZH

= V

–

0.1

µA

= V

(50-k

Ω

pull-down)

200

OZL

= V

-10

-0.1

–

Stand-by current

[3]

RAM/ROM should be in powerdown mode.

DDQ

Output open, V

= V

, V

= V

Design Dependent

µA

MSM13Q0000/14Q0000

Oki Semiconductor

AC Characteristics (V

= 3.3 V, V

= 0 V, T

= 25°C)

Parameter

Driving

Type

Conditions

[1]

[2]

1. Input transition time in 0.2 ns / 3.3 V.

2. Typical condition is V

= 3.3 V and T

= 25

Rated Value

[3]

3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process.

Unit

Internal gate

propagation delay

Inverter

F/O = 2, L = 0 mm

= 3.3 V

0.082

0.068

0.062

2-input NAND

0.14

0.13

2-input NOR

0.16

0.14

Inverter

F/O = 2, L = 1 mm

= 3.3 V

0.19

0.13

0.097

2-input NAND

0.28

0.20

2-input NOR

0.34

0.24

Toggle frequency

F/O= 1, L = 0 mm

1040

MHz

Input buffer

propagation delay

TTL level normal input buffer

F/O = 2,L = 1 mm

0.35

TTL level 5-V tolerant buffer

0.64

Output buffer

propagation delay

Push-pull

Normal output

buffer

4 mA

CL = 20pF

2.15

8 mA

CL= 50 pF

2.25

12 mA

CL = 100 pF

2.82

3-state

5-V tolerant

buffer

4 mA

CL = 20 pF

2.41

Output buffer

transition times

[4]

4. Output rising and falling times are both specified over a 10 to 90% range.

Push-pull

Normal output

buffer

12 mA

CL = 100 pF

4.68 (r)

3.48 (f)

3-state

5-V tolerant

buffer

4 mA

CL = 20 pF

3.53 (r)

3.24 (f)

MSM13Q0000/14Q0000

Oki Semiconductor

MACRO LIBRARY

Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard

macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following

figure illustrates the main classes of macrocells and macrofunctions available.

Examples

[1] Under development

Figure 3. Oki Macrocell and Macrofunction Library

Macro Library

Macrocells

Basic Macrocells

with Scan test

Clock Tree Driver

Macrocells

3V, 5V Tolerant

Output Macrocells

MSI Macrocells

Mega/Special

Macrocells

[1]

3-V, 5-V Tolerant

Input Macrocells

3-V, 5-V Tolerant

Bi-Directional

Macrocells

MSI

Macrofunctions

Oscillator

Macrocells

Macrofunctions

NANDs

NORs

EXORs

Latches

Flip-Flops

3-State Outputs

Push-Pull Outputs

PECL Outputs

Counters

Shift Registers

UART

PLL

Inputs

Inputs with Pull-Ups

Gated Oscillators

Open Drain Outputs

Slew Rate Control Outputs

PCI Outputs

Inputs with Pull-Downs

PECL Inputs

I/O

PCI I/O

I/O with Pull-Downs

I/O with Pull-Ups

CBA RAMs:

Single-Port RAMs (asynchronous or synchronous)

Dual-Port RAMs (asynchronous)

Memory

Macrocells

Flip-Flops

Combinational Logic

USB Controller

Ethernet Controller

4-Bit Register/Latches

MSM13Q0000/14Q0000

Oki Semiconductor

Macrocells for Driving Clock Trees

Oki offers H-clock-tree drivers that minimize clock skew. The advanced layout software uses dynamic

driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular cir-

cuit. Features of the H-clock-tree driver-macrocells include:

• True RC back annotation of the clock network

• Automatic fan-out balancing

• Dynamic sub-trunk allocation

• Single clock tree driver logic symbol

• Automatic branch length minimization

• Dynamic driver placement

• Allows multiple clock trees

Clock

Figure 4. H-Clock-Tree Structure

MSM13Q0000/14Q0000

Oki Semiconductor

OKI ADVANCED DESIGN CENTER CAD TOOLS

Oki’s advanced design center CAD tools include support for the following:

• Floorplanning for front-end simulation, back-end layout control, and link to synthesis

• Clock tree structures improve first-time silicon success by eliminating clock skew problems

• JTAG Boundary scan support

• Power calculation which predicts circuit power under simulation conditions to accurately model

package requirements (in development)