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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3–41

REV 5

Motorola, Inc. 1996

3/93

Bi-Quinary Counter

The MC10138 is a four bit counter capable of divide by two, five, or ten

functions. It is composed of four set–reset master–slave flip–flops. Clock

inputs trigger on the positive going edge of the clock pulse.

Set or reset input override the clock, allowing asynchronous “set” or

“clear.” Individual set and common reset inputs are provided, as well as

complementary outputs for the first and fourth bits.

PD = 370 mW typ/pkg (No Load)

ftog = 150 MHz typ

tr, tf = 2.5 ns typ (20%–80%)

LOGIC DIAGRAM

VCC1 = PIN 1; VCC2 = PIN 16; VEE = PIN 8

Clock

Reset

Q’

COUNTER TRUTH TABLES

BI–QUINARY

(Clock connected to C2

and Q3 connected to C1)

BCD

(Clock connected to C1

and Q0 connected to C2)

COUNT

COUNTER STATE DIAGRAM — POSITIVE LOGIC

CLOCK CONNECTED TO C2

Q0 CONNECTED TO C2

MC10138

DIP

PIN ASSIGNMENT

VCC1

VEE

VCC2

RESET

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08

FN SUFFIX

PLCC

CASE 775–02

Pin assignment is for Dual–in–Line Package.

For PLCC pin assignment, see the Pin Conversion

Tables on page 6–11 of the Motorola MECL Data

Book (DL122/D).

MC10138

MOTOROLA

MECL Data

DL122 — Rev 6

3–42

ELECTRICAL CHARACTERISTICS

Test Limits

Pin

Under

–30

+25

+85

Characteristic

Symbol

Under

Test

Min

Max

Min

Typ

Max

Min

Max

Unit

Power Supply Drain Current

mAdc

Input Current

IinH

5,6,10,11

350

390

460

650

220

245

290

410

220

245

290

Adc

IinL

All

0.5

0.3

Adc

Output Voltage

Logic 1

VOH

3,14

(3.)

2,4,13,15

(2.)

–1.060

–0.890

–0.960

–0.810

–0.890

–0.700

Vdc

Output Voltage

Logic 0

VOL

3,14

(2.)

2,4,13,15

(3.)

–1.890

–1.675

–1.850

–1.650

–1.825

–1.615

Vdc

Threshold Voltage

Logic 1

VOHA

2,4,13,15

(2.)

3,14

(3.)

13,15

(2.)

–1.080

–0.980

–0.910

Vdc

Threshold Voltage

Logic 0

VOLA

2,4,13,15

(3.)

3,14

(2.)

13,15

(3.)

–1.655

–1.630

–1.595

Vdc

Switching Times

(50

Ω

Load)

Propagation

Clock Delays

Delay

t12+15+

t12+14+

t7+13+

t7+4+

t7+2+

t7+3+

1.4

5.0

5.2

1.5

3.5

4.8

5.0

1.5

5.3

5.5

t12+15–

t12+14–

t7+13–

t7+4–

t7+2–

t7+3–

1.4

5.0

5.2

1.5

3.5

4.8

5.0

1.5

5.3

5.5

Set Delay

t11+15+

t11+14–

1.4

5.2

1.5

5.0

1.5

5.5

Reset Delay

t9+14+

t9+15–

1.4

5.2

1.5

5.0

1.5

5.5

Rise Time

(20 to 80%)

t14+

t15+

1.1

4.7

1.1

2.5

4.5

1.1

5.0

Fall Time

(20 to 80%)

t14–

t15–

1.1

4.7

1.1

2.5

4.5

1.1

5.0

Counting Frequency

fcount

125

150

125

MHz

1. Individually test each input; apply VILmin to pin under test.

2. Set all four flip–flops by applying pulse

VIHmax

VILmin

to pins 5, 6, 10, and 11 prior to applying test voltage indicated.

3. Reset all four flip–flops by applying pulse

VIHmax

VILmin

to pin 9 prior to applying test voltage indicated.

MC10138

3–43

MOTOROLA

MECL Data

DL122 — Rev 6

ELECTRICAL CHARACTERISTICS

(continued)

NOTE: Each MECL 10,000 series circuit has

been designed to meet the dc specifications

TEST VOLTAGE VALUES (Volts)

been designed to meet the dc specifications

shown in the test table, after thermal equilibrium

has been established. The circuit is in a test

@ Test Temperature

VIHmax

VILmin

VIHAmin

VILAmax

VEE

has been established. The circuit is in a test

socket or mounted on a printed circuit board and

transverse air flow greater than 500 linear fpm is

–30

–0.890

–1.890

–1.205

–1.500

–5.2

transverse air flow greater than 500 linear fpm is

maintained. Outputs are terminated through a

50–ohm resistor to –2.0 volts. Test procedures

are shown for only one gate The other gates are

+25

–0.810

–1.850

–1.105

–1.475

–5.2

are shown for only one gate. The other gates are

tested in the same manner.

+85

–0.700

–1.825

–1.035

–1.440

–5.2

Pin

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

Characteristic

Symbol

Pin

Under

Test

VIHmax

VILmin

VIHAmin

VILAmax

VEE

(VCC)

Gnd

Power Supply Drain Current

1, 16

Input Current

IinH

5,6,10,11

1, 16

IinL

All

Note 1.

1, 16

Output Voltage

Logic 1

VOH

3,14

(3.)

2,4,13,15

(2.)

5,6,10,11

1, 16

Output Voltage

Logic 0

VOL

3,14

(2.)

2,4,13,15

(3.)

5,6,10,11

1, 16

Threshold Voltage

Logic 1

VOHA

2,4,13,15

(2.)

3,14

(3.)

13,15

(2.)

5,6,10,11

7,12

1, 16

Threshold Voltage

Logic 0

VOLA

2,4,13,15

(3.)

3,14

(2.)

13,15

(3.)

5,6,10,11

7,12

1, 16

Switching Times

(50

Ω

Load)

Pulse In

Pulse Out

–3.2 V

+2.0 V

Propagation Delay

Clock Delays

t12+15+

t12+14+

t7+13+

t7+4+

t7+2+

t7+3+

1, 16

t12+15–

t12+14–

t7+13–

t7+4–

t7+2–

t7+3–

1, 16

Set Delay

t11+15+

t11+14–

1, 16

Reset Delay

t9+14+

t9+15–

1, 16

Rise Time

(20 to 80%)

t14+

t15+

1, 16

Fall Time

(20 to 80%)

t14–

t15–

1, 16

Counting Frequency

fcount

1, 16

1. Individually test each input; apply VILmin to pin under test.

2. Set all four flip–flops by applying pulse

VIHmax

VILmin

to pins 5, 6, 10, and 11 prior to applying test voltage indicated.

3. Reset all four flip–flops by applying pulse

VIHmax

VILmin

to pin 9 prior to applying test voltage indicated.

MC10138

MOTOROLA

MECL Data

DL122 — Rev 6

3–44

OUTLINE DIMENSIONS

FN SUFFIX

PLASTIC PLCC PACKAGE

CASE 775–02

ISSUE C

NOTES:

1. DATUMS –L–, –M–, AND –N– DETERMINED

WHERE TOP OF LEAD SHOULDER EXITS PLASTIC

BODY AT MOLD PARTING LINE.

2. DIMENSION G1, TRUE POSITION TO BE

MEASURED AT DATUM –T–, SEATING PLANE.

3. DIMENSIONS R AND U DO NOT INCLUDE MOLD

FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)

PER SIDE.

4. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

5. CONTROLLING DIMENSION: INCH.

6. THE PACKAGE TOP MAY BE SMALLER THAN THE

PACKAGE BOTTOM BY UP TO 0.012 (0.300).

DIMENSIONS R AND U ARE DETERMINED AT THE

OUTERMOST EXTREMES OF THE PLASTIC BODY

EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,

GATE BURRS AND INTERLEAD FLASH, BUT

INCLUDING ANY MISMATCH BETWEEN THE TOP

AND BOTTOM OF THE PLASTIC BODY.

7. DIMENSION H DOES NOT INCLUDE DAMBAR

PROTRUSION OR INTRUSION. THE DAMBAR

PROTRUSION(S) SHALL NOT CAUSE THE H

DIMENSION TO BE GREATER THAN 0.037 (0.940).

THE DAMBAR INTRUSION(S) SHALL NOT CAUSE

THE H DIMENSION TO BE SMALLER THAN 0.025

(0.635).

–M–

–N–

–L–

Y BRK

L–M

0.007 (0.180)

L–M

0.007 (0.180)

L–M

0.010 (0.250)

VIEW D–D

L–M

0.007 (0.180)

L–M

0.007 (0.180)

L–M

0.010 (0.250)

VIEW S

0.004 (0.100)

–T–

SEATING

PLANE

L–M

0.007 (0.180)

L–M

0.007 (0.180)

VIEW S

DIM

MIN

MAX

MIN

MAX

MILLIMETERS

INCHES

0.385

0.395

9.78

10.03

0.385

0.395

9.78

10.03

0.165

0.180

4.20

4.57

0.090

0.110

2.29

2.79

0.013

0.019

0.33

0.48

0.050 BSC

1.27 BSC

0.026

0.032

0.66

0.81

0.020

–––

0.51

–––

0.025

–––

0.64

–––

0.350

0.356

8.89

9.04

0.350

0.356

8.89

9.04

0.042

0.048

1.07

1.21

0.042

0.048

1.07

1.21

0.042

0.056

1.07

1.42

–––

0.020

–––

0.50

0.310

0.330

7.88

8.38

0.040

–––

1.02

–––

MC10138

3–45

MOTOROLA

MECL Data

DL122 — Rev 6

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

16 PL

SEATING

PLANE

–T–

0.25 (0.010)

DIM

MIN

MAX

MIN

MAX

MILLIMETERS

INCHES

0.740

0.770

18.80

19.55

0.250

0.270

6.35

6.85

0.145

0.175

3.69

4.44

0.015

0.021

0.39

0.53

0.040

0.70

1.02

1.77

0.100 BSC

2.54 BSC

0.050 BSC

1.27 BSC

0.008

0.015

0.21

0.38

0.110

0.130

2.80

3.30

0.295

0.305

7.50

7.74

0.020

0.040

0.51

1.01