DATA SHEET
Product specification
File under Integrated Circuits, IC06
1999 Sep 20
INTEGRATED CIRCUITS
74AHC1G86; 74AHCT1G86
2-input EXCLUSIVE-OR gate
1999 Sep 20
2
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74AHC1G86; 74AHCT1G86
FEATURES
•
Symmetrical output impedance
•
High noise immunity
•
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
•
Low power dissipation
•
Balanced propagation delays
•
Very small 5-pin package
•
Output capability: standard.
DESCRIPTION
The 74AHC1G/AHCT1G86 is a
high-speed Si-gate CMOS device.
The 74AHC1G/AHCT1G86 provides
the 2-input EXCLUSIVE-OR function.
QUICK REFERENCE DATA
Ground = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µ
W).
P
D
= C
PD
×
V
CC
2
×
f
i
+ (C
L
×
V
CC
2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
2. The condition is V
I
= GND to V
CC
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC1G
AHCT1G
t
PHL
/t
PLH
propagation delay
inA, inB to outY
C
L
= 15 pF;
V
CC
= 5 V
3.4
3.5
ns
C
I
input capacitance
1.5
1.5
pF
C
PD
power dissipation
capacitance
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
9
11
pF
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level.
ORDERING INFORMATION
INPUTS
OUTPUT
inA
inB
outY
L
L
L
L
H
H
H
L
H
H
H
L
TYPE NUMBER
PACKAGES
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
MARKING
74AHC1G86GW
−
40 to +85
°
C
5
SC-88A
plastic
SOT353
AH
74AHCT1G86GW
5
SC-88A
plastic
SOT353
CH
1999 Sep 20
3
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74AHC1G86; 74AHCT1G86
PINNING
PIN
SYMBOL
DESCRIPTION
1
inA
data input
2
inB
data input
3
GND
ground (0 V)
4
outY
data output
5
V
CC
DC supply voltage
Fig.1 Pin configuration.
handbook, halfpage
1
2
3
5
4
MNA037
86
VCC
inB
outY
GND
inA
Fig.2 Logic symbol.
handbook, halfpage
MNA038
inA
inB
outY
2
1
4
Fig.3 IEC logic symbol.
handbook, halfpage
1
2
= 1
4
MNA039
Fig.4 Logic diagram.
handbook, halfpage
MNA040
outY
inA
inB
1999 Sep 20
4
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74AHC1G86; 74AHCT1G86
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55
°
C the value of P
D
derates linearly with 2.5 mW/K.
SYMBOL
PARAMETER
CONDITIONS
74AHC1G
74AHCT1G
UNIT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
V
CC
DC supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
V
I
input voltage
0
−
5.5
0
−
5.5
V
V
O
output voltage
0
−
V
CC
0
−
V
CC
V
T
amb
operating ambient
temperature
see DC and AC
characteristics per
device
−
40
+25
+85
−
40
+25
+85
°
C
t
r
,t
f
(
∆
t/
∆
f) input rise and fall times
except for
Schmitt trigger inputs
V
CC
= 3.3
±
0.3 V
−
−
100
−
−
−
ns/V
V
CC
= 5
±
0.5 V
−
−
20
−
−
20
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CC
DC supply voltage
−
0.5
+7.0
V
V
I
input voltage
−
0.5
+7.0
V
I
IK
DC input diode current
V
I
<
−
0.5
−
−
20
mA
I
OK
DC output diode current
V
O
<
−
0.5 or V
O
> V
CC
+ 0.5 V; note 1
−
±
20
mA
I
O
DC output source or sink current
−
0.5 V < V
O
< V
CC
+ 0.5 V
−
±
25
mA
I
CC
DC V
CC
or GND current
−
±
75
mA
T
stg
storage temperature
−
65
+150
°
C
P
D
power dissipation per package
temperature range:
−
40 to +85
°
C; note 2
−
200
mW
1999 Sep 20
5
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74AHC1G86; 74AHCT1G86
DC CHARACTERISTICS
Family 74AHC1G
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
°
C)
UNIT
OTHER
V
CC
(V)
25
−
40 to +85
MIN.
TYP.
MAX.
MIN.
MAX.
V
IH
HIGH-level input voltage
2.0
1.5
−
−
1.5
−
V
3.0
2.1
−
−
2.1
−
5.5
3.85
−
−
3.85
−
V
IL
LOW-level input voltage
2.0
−
−
0.5
−
0.5
V
3.0
−
−
0.9
−
0.9
5.5
−
−
1.65
−
1.65
V
OH
HIGH-level output
voltage; all outputs
V
I
= V
IH
or V
IL
;
I
O
=
−
50
µ
A
2.0
1.9
2.0
−
1.9
−
V
3.0
2.9
3.0
−
2.9
−
4.5
4.4
4.5
−
4.4
−
HIGH-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
=
−
4.0 mA
3.0
2.58
−
−
2.48
−
V
V
I
= V
IH
or V
IL
;
I
O
=
−
8.0 mA
4.5
3.94
−
−
3.8
−
V
OL
LOW-level output
voltage; all outputs
V
I
= V
IH
or V
IL
;
I
O
= 50
µ
A
2.0
−
0
0.1
−
0.1
V
3.0
−
0
0.1
−
0.1
4.5
−
0
0.1
−
0.1
LOW-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
= 4.0 mA
3.0
−
−
0.36
−
0.44
V
V
I
= V
IH
or V
IL
;
I
O
= 8.0 mA
4.5
−
−
0.36
−
0.44
I
I
input leakage current
V
I
= V
CC
or GND
5.5
−
−
0.1
−
1.0
µ
A
I
CC
quiescent supply
current
V
I
= V
CC
or GND;
I
O
= 0
5.5
−
−
1.0
−
10
µ
A
C
I
input capacitance
−
1.5
10
−
10
pF
1999 Sep 20
6
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74AHC1G86; 74AHCT1G86
Family 74AHCT1G
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
°
C)
UNIT
OTHER
V
CC
(V)
25
−
40 to +85
MIN.
TYP.
MAX.
MIN.
MAX.
V
IH
HIGH-level input voltage
4.5 to 5.5 2.0
−
−
2.0
−
V
V
IL
LOW-level input voltage
4.5 to 5.5
−
−
0.8
−
0.8
V
V
OH
HIGH-level output
voltage; all outputs
V
I
= V
IH
or V
IL
;
I
O
=
−
50
µ
A
4.5
4.4
4.5
−
4.4
−
V
HIGH-level output
voltage
V
I
= V
IH
or V
IL
;
I
O
=
−
8.0 mA
4.5
3.94
−
−
3.8
−
V
V
OL
LOW-level output
voltage; all outputs
V
I
= V
IH
or V
IL
;
I
O
= 50
µ
A
4.5
−
0
0.1
−
0.1
V
LOW-level output voltage V
I
= V
IH
or V
IL
;
I
O
= 8.0 mA
4.5
−
−
0.36
−
0.44
V
I
I
input leakage current
V
I
= V
IH
or V
IL
5.5
−
−
0.1
−
1.0
µ
A
I
CC
quiescent supply current
V
I
= V
CC
or GND;
I
O
= 0
5.5
−
−
1.0
−
10
µ
A
∆
I
CC
additional quiescent
supply current per input
pin
V
I
= 3.4 V;
other inputs at
V
CC
or GND; I
O
= 0
5.5
−
−
1.35
−
1.5
mA
C
I
input capacitance
−
1.5
10
−
10
pF
1999 Sep 20
7
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74AHC1G86; 74AHCT1G86
AC CHARACTERISTICS
Type 74AHC1G86
Ground = 0 V; t
r
= t
f
≤
3.0 ns.
Notes
1. Typical values at V
CC
= 3.3 V.
2. Typical values at V
CC
= 5.0 V.
74AHCT1G86
Ground = 0 V; t
r
= t
f
≤
3.0 ns.
Note
1. Typical values at V
CC
= 5.0 V.
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
°
C)
UNIT
WAVEFORMS
C
L
25
−
40 to +85
MIN.
TYP.
MAX.
MIN.
MAX.
V
CC
= 3.0 to 3.6 V; note 1
t
PHL
/t
PLH
propagation delay
inA, inB to outY
see Figs 5 and 6
15 pF
−
4.0
11.0
1.0
13
ns
50 pF
−
5.8
14.5
1.0
16.5
ns
V
CC
= 4.5 to 5.5 V; note 2
t
PHL
/t
PLH
propagation delay
inA, inB to outY
see Figs 5 and 6
15 pF
−
3.4
6.8
1.0
8.0
ns
50 pF
−
4.9
8.8
1.0
10.0
ns
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
(
°
C)
UNIT
WAVEFORMS
C
L
25
−
40 to +85
MIN.
TYP.
MAX.
MIN.
MAX.
V
CC
= 4.5 to 5.5 V; note 1
t
PHL
/t
PLH
propagation delay
inA, inB to outY
see Figs 5 and 6
15 pF
−
3.5
6.9
1.0
8.0
ns
50 pF
−
5.0
7.9
1.0
9.0
ns
1999 Sep 20
8
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74AHC1G86; 74AHCT1G86
AC WAVEFORMS
Fig.5 The input (inA, inB) to output (outY) propagation delays.
handbook, halfpage
MNA041
tPHL
tPLH
VM
VM
inA, inB input
outY output
FAMILY
V
I
INPUT
REQUIREMENTS
V
M
INPUT
V
M
OUTPUT
AHC1G
GND to V
CC
50% V
CC
50% V
CC
AHCT1G
GND to 3.0 V
1.5 V
50% V
CC
Fig.6 Load circuitry for switching times.
Definitions for test circuit:
C
L
= load capacitance including jig and probe capacitance
(see “AC characteristics” for values).
R
T
= termination resistance should be equal to the output
impedance Z
o
of the pulse generator.
handbook, halfpage
VCC
VI
VO
MNA034
D.U.T.
CL
50 pF
RT
PULSE
GENERATOR
1999 Sep 20
9
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74AHC1G86; 74AHCT1G86
PACKAGE OUTLINE
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
EIAJ
SOT353
w
B
M
bp
D
e1
e
A
A1
Lp
Q
detail X
HE
E
v
M
A
A
B
y
0
1
2 mm
scale
c
X
1
3
2
4
5
Plastic surface mounted package; 5 leads
SOT353
UNIT
A1
max
bp
c
D
E
(2)
e
1
HE
Lp
Q
y
w
v
mm
0.1
0.30
0.20
2.2
1.8
0.25
0.10
1.35
1.15
0.65
e
1.3
2.2
2.0
0.2
0.1
0.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15
0.25
0.15
A
1.1
0.8
97-02-28
SC-88A
1999 Sep 20
10
Philips Semiconductors
Product specification
2-input EXCLUSIVE-OR gate
74AHC1G86; 74AHCT1G86
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical reflow peak temperatures range from
215 to 250
°
C. The top-surface temperature of the
packages should preferable be kept below 230
°
C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•