MCM56824A
1
MOTOROLA FAST SRAM
DSPRAM
™
8K x 24 Bit Fast Static RAM
The MCM56824A is a 196,608 bit static random access memory organized as
8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple
chip enable inputs, output enable, and an externally controlled single address pin
multiplexer. These functions allow for direct connection to the Motorola
DSP56001 Digital Signal Processor and provide a very efficient means for imple-
mentation of a reduced parts count system requiring no additional interface logic.
The availability of multiple chip enable (E1 and E2) and output enable (G) in-
puts provides for greater system flexibility when multiple devices are used. With
either chip enable input unasserted, the device will enter standby mode, useful
in low–power applications. A single on–chip multiplexer selects A12 or X/Y as the
highest order address input depending upon the state of the V/S control input.
This feature allows one physical static RAM component to efficiently store pro-
gram and vector or scalar operands by dynamically re–partitioning the RAM
array. Typical applications will logically map vector operands into upper memory
with scalar operands being stored in lower memory. By connecting
DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control
pin, such partitioning can occur with no additional components. This al-
lows efficient utilization of the RAM resource irrespective of operand
type. See application diagrams at the end of this document for addition-
al information.
Multiple power and ground pins have been utilized to minimize effects
induced by output noise.
The MCM56824A is available in a 52 pin plastic leaded chip–carrier
(PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA.
•
Single 5 V
±
10% Power Supply
•
Fast Access and Cycle Times: 20/25/35 ns Max
•
Fully Static Read and Write Operations
•
Equal Address and Chip Enable Access Times
•
Single Bit On–Chip Address Multiplexer
•
Active High and Active Low Chip Enable Inputs
•
Output Enable Controlled Three State Outputs
•
High Board Density PLCC Package
•
Low Power Standby Mode
•
Fully TTL Compatible
DSPRAM is a trademark of Motorola, Inc.
For proper operation of the device, all VSS
pins must be connected to ground.
PIN NAMES
A0 – A11
Address Inputs
. . . . . . . . . . . . . . .
A12, X/Y
Multiplexed Address
. . . . . . . . . .
V/S
Address Multiplexer Control
. . . . . . . . .
W
Write Enable
. . . . . . . . . . . . . . . . . . . . . . .
E1, E2
Chip Enable
. . . . . . . . . . . . . . . . . . .
G
Output Enable
. . . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ23
Data Input/Output
. . . . . . . . . .
VCC
+5 V Power Supply
. . . . . . . . . . . . . . .
VSS
Ground
. . . . . . . . . . . . . . . . . . . . . . . . . .
NC
No Connection
. . . . . . . . . . . . . . . . . . . .
PIN ASSIGNMENTS
DQ0
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ23
DQ22
DQ21
VSS
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
VSS
DQ14
DQ13
DQ1
1
A9
A8
A7
A6
DQ12
NC
W
G
CC
SS
E1
E2
V
V
8
9
10
11
12
13
14
15
16
17
18
19
20
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
49
50
51
52
1
2
3
4
5
6
7
33
32
31
30
29
28
27
26
25
24
23
22
21
A10
A1
1
A12
A5
A4
A3
A2
A1
A0
CC
V
NC
X/Y
V/S
PLCC
D21
VSS
VSS
A0
VCC
NC
X/Y
A11
A2
A4
A3
D23
A1
V/S
A12
A10
D0
D22
D20
D17
D16
D15
D14
D13
D12
D1
D2
VSS
D5
D8
D7
VSS
D9
D11
D10
E2
A6
A8
W
E1
VCC
G
A7
A9
VSS
A5
D18
D19
VSS
D3
D4
D6
9
8
7
6
5
4
10
B
C
G
A
D
E
F
H
J
Not to Scale
3
2
1
VIEW OF PBGA PACKAGE BOTTOM
Order this document
by MCM56824A/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM56824A
FN PACKAGE
52–LEAD PLCC
CASE 778–02
9 x 10 GRID
86 BUMP PBGA
CASE 896A–01
REV 2
4/95
©
Motorola, Inc. 1995
MCM56824A
2
MOTOROLA FAST SRAM
BLOCK DIAGRAM
Q
0
1
INPUT
DATA
CONTROL
(MSB)
(LSB)
V/S
A9
A6
DQ23
MEMORY ARRAY
512 ROWS x
384 COLUMNS
ROW
DECODER
COLUMN DECODER
COLUMN I/O
VCC
A11
A10
A5
A0
A12
X/Y
G
W
E1
E2
DQ0
A12
2 TO 1 MUX
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
VSS
TRUTH TABLE
E1
E2
G
W
V/S
Mode
Supply
Current
I/O
Status
H
X
X
X
X
Not Selected
ISB
High–Z
X
L
X
X
X
Not Selected
ISB
High–Z
L
H
H
H
X
Output Disable
ICC
High–Z
L
H
L
H
H
Read Using X/Y
ICC
Data Out
L
H
L
H
L
Read Using A12
ICC
Data Out
L
H
X
L
H
Write Using X/Y
ICC
Data In
L
H
X
L
L
Write Using A12
ICC
Data In
NOTE: X=don’t care.
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS = 0 V)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
– 0.5 to + 7.0
V
Voltage Relative to VSS for Any Pin
Except VCC
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
±
20
mA
Power Dissipation
PD
1.75
W
Temperature Under Bias
Tbias
– 10 to + 85
°
C
Operating Temperature
TA
0 to + 70
°
C
Storage Temperature
Tstg
– 55 to + 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect
against damage due to high static voltages
or electric fields; however, it is advised that
normal precautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to this high–impedance
circuit.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equi-
librium has been established. The circuit is
assumed to be in a test socket or mounted
on a printed circuit board with at least 300
LFPM of transverse air flow being
maintained.
MCM56824A
3
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.2
—
VCC + 0.3
V
Input Low Voltage
VIL
– 0.5*
—
0.8
V
* VIL (min) = – 3.0 V ac (pulse width
≤
20 ns)
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(i)
—
±
1.0
µ
A
Output Leakage Current (G = VIH, E1 = VIH, E2 = VIL, Vout = 0 to VCC)
Ilkg(O)
—
±
1.0
µ
A
AC Supply Current (G = VIH, E1 = VIL, E2 = VIH, Iout = 0 mA,
All Other Inputs
≥
VIL = 0.0 V and VIH
≥
3.0 V)
MCM56824A–20 Cycle Time:
≥
20 ns
MCM56824A–25 Cycle Time:
≥
25 ns
MCM56824A–35 Cycle Time:
≥
35 ns
ICCA
—
—
—
260
220
180
mA
Standby Current (E1 = VIH, E2 = VIL, All Inputs = VIL or VIH)
ISB1
—
15
mA
CMOS Standby Current (E1
≥
VCC – 0.2 V, E2
≤
0.2 V, All Inputs
≥
VCC – 0.2 V or
≤
0.2 V)
ISB2
—
10
mA
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25
°
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
All Pins Except DQ0 – DQ23
Cin
4
6
pF
Input/Output Capacitance
DQ0 – DQ23
Cout
6
8
pF
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
(a)
(b)
5 pF
+ 5 V
OUTPUT
255
Ω
480
Ω
Figure 1. AC Test Loads
MCM56824A
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
3 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
See Figure 1a Unless Otherwise Noted
. . . . . . . . . . . . .
READ CYCLE TIMING
(See Notes 1, 2, and 3)
MCM56824A–20
MCM56824A–25
MCM56824A–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
20
—
25
—
35
—
ns
Address Access Time
tAVQV
—
20
—
25
—
35
ns
MUX Control Valid to Output Valid
tVSVQV
—
20
—
25
—
35
ns
Chip Enable to Output Valid
tE1LQV
tE2HQV
—
20
—
25
—
35
ns
4
Output Enable to Output Valid
tGLQV
—
8
—
10
—
15
ns
Output Active from Chip Enable
tE1LQX
tE2HQX
2
—
2
—
0
—
ns
4, 5
Output Active from Output Enable
tGLQX
0
—
0
—
0
—
ns
5
Output Hold from Address Change
tAXQX
4
—
5
—
5
—
ns
Output Hold from MUX Control Change
tVSXQX
4
—
5
—
5
—
ns
Chip Enable to Output High–Z
tE1HQZ
tE2LQZ
0
10
0
15
0
15
ns
4, 5
Output Enable High to Output High–Z
tGHQZ
0
8
0
15
0
15
ns
5
NOTES:
1. A read cycle is defined by W high.
2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition.
3. Addresses valid prior to or coincident with E1 going low or E2 going high.
4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
5. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than
tGLQX min for a given device and from device to device.
READ CYCLE
tAVQV
HIGH–Z
HIGH–Z
Q (DATA OUT)
G (OUTPUT ENABLE)
E1 (CHIP ENABLE)
V/S (MUX CONTROL)
A (ADDRESS)
tVSXQX
tGHQZ
tE1HQZ
DATA VALID
tE1LQX
tE1LQV
tGLQV
tVSVQV
tAVAV
tAXQX
tGLQX
MCM56824A
5
MOTOROLA FAST SRAM
WRITE CYCLE TIMING
(Write Enable Initiated, See Note 1)
MCM56824A–20
MCM56824A–25
MCM56824A–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
20
—
25
—
35
—
ns
Address Setup Time
tAVWL
0
—
0
—
0
—
ns
2
MUX Control Setup Time
tVSVWL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVWH
15
—
20
—
30
—
ns
MUX Control Valid to End of Write
tVSVWH
15
—
20
—
30
—
ns
Write Pulse Width
tWLWH
15
—
15
—
20
—
ns
3
Write Enable to Chip Enable Disable
tWLE1H
tWLE2L
15
—
15
—
20
—
ns
3, 4
Chip Enable to End of Write
tE1LWH
tE2HWH
15
—
15
—
20
—
ns
3, 4
Data Valid to End of Write
tDVWH
8
—
10
—
15
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
ns
5
Write Recovery Time
tWHAX
0
—
0
—
0
—
ns
2
MUX Control Recovery Time
tWHVSX
0
—
0
—
0
—
ns
Write High to Output Low–Z
tWHQX
4
—
5
—
5
—
ns
6
Write Low to Output High–Z
tWLQZ
0
15
0
15
0
15
ns
6
NOTES:
1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2
low.
2. Write must be high for all address transitions.
3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state.
4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
5. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than
tGLQX min for a given device and from device to device.
WE INITIATED WRITE CYCLE
HIGH–Z
HIGH–Z
E1 (CHIP ENABLE)
VALID DATA IN
D (DATA IN)
W (WRITE ENABLE)
V/S (MUX CONTROL)
Q (DATA OUT)
A (ADDRESS)
tAVAV
tWHQX
tDVWH
tWLQZ
tWHAX
tWHDX
tWHVSX
tAVWL
tE1LWH
tVSVWL
tWLWH
tVSVWH
tAVWH
tWLE1H
MCM56824A
6
MOTOROLA FAST SRAM
WRITE CYCLE TIMING
(Chip Enable Initiated, See Note 1)
MCM56824A–20
MCM56824A–25
MCM56824A–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
20
—
25
—
35
—
ns
Address Setup Time
tAVE1L
tAVE2H
0
—
0
—
0
—
ns
2
MUX Control Setup Time
tVSVE1L
tVSVE2H
0
—
0
—
0
—
ns
2
Address Valid to End of Write
tAVE1H
tAVE2L
15
—
20
—
30
—
ns
2
MUX Control Valid to End of Write
tVSVE1H
tVSVE2L
15
—
20
—
30
—
ns
2
Chip Enable to End of Write
tE1LE1H
tE2HE2L
12
—
15
—
20
—
ns
2, 3
Data Valid to End of Write
tDVE1H
tDVE2L
8
—
10
—
15
—
ns
2
Data Hold Time
tE1HDX
tE2LDX
0
—
0
—
0
—
ns
2, 4
Write Recovery Time
tE1HAX
tE2LAX
0
—
0
—
0
—
ns
2
MUX Control Recovery Time
tE1HVSX
tE2LVSX
0
—
0
—
0
—
ns
2
NOTES:
1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2
low.
2. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state.
4. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
E1 OR E2 INITIATED WRITE CYCLE
D (DATA IN)
W (WRITE ENABLE)
E1 (CHIP ENABLE)
V/S (MUX CONTROL)
Q (DATA OUT)
A (ADDRESS)
tAVAV
tAVE1H
tE1HAX
tVSVE1H
tE1HVSX
tE1LE1H
tVSVE1L
tDVE1H
tE1HDX
DATA VALID
HIGH–Z
tAVE1L
MCM56824A
7
MOTOROLA FAST SRAM
RAM A12
A0 – A11
A12
X/Y
A0 – A11
8K x 24
“X” OPERANDS
MCM56824A
DSP56001
PROGRAM
MEMORY
4K x 24
“X” OPERANDS
PROGRAM
MEMORY
HIGH
4K x 24
“Y” OPERANDS
PROGRAM
MEMORY
LOW
V/S = “1”
V/S = “0”
V/S
MUX
DSPRAM Multiplexed Vector/Scalar Address Maps
8K x 24 DSPRAM Used in Typical Application
X/Y
A0 – A11
D0 – D23
A0 – A11
D0 – D23
WR
A15
V/S
W
X/Y
MEMORY
MANAGEMENT
PINS
A12
A12
MCM56824A
DSP56001
ORDERING INFORMATION
(Order by Full Part Number)
MCM
56824A
XX
XX XX
Motorola Memory Prefix
Part Number
Full Part Numbers — MCM56824AFN20
MCM56824AFN25
MCM56824AFN35
MCM56824AZP20
MCM56824AZP25
MCM56824AZP35
MCM56824AZP20R2 MCM56824AZP25R2
MCM56824AZP35R2
Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns)
Package (FN = PLCC, ZP = PBGA)
Shipping Method (R2 = Tape and Reel, Blank = rails)
MCM56824A
8
MOTOROLA FAST SRAM
ZP PACKAGE
9 x 10 PBGA
CASE 896A–01
PACKAGE DIMENSIONS
-T-
-B-
B
-A-
A
R
N
L
C
G
A
B
C
D
E