MCM6246
1
MOTOROLA FAST SRAM
512K x 8 Bit Static Random
Access Memory
The MCM6246 is a 4,194,304 bit static random access memory organized as
524,288 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes, while CMOS circuitry reduces power consumption and provides
for greater reliability.
The MCM6246 is equipped with chip enable (E) and output enable (G) pins,
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high impedance.
The MCM6246 is available in a 400 mil, 36–lead surface–mount SOJ package.
•
Single 5 V
±
10% Power Supply
•
Fast Access Time: 17/20/25/35 ns
•
Equal Address and Chip Enable Access Time
•
All Inputs and Outputs are TTL Compatible
•
Three–State Outputs
•
Power Operation: 205/200/185/170 mA Maximum, Active AC
BLOCK DIAGRAM
G
A
A
A
A
A
A
A
A
A
MEMORY MATRIX
1024 ROWS x
4096 COLUMNS
ROW
DECODER
INPUT
DATA
CONTROL
A
A
A
A
A
A
A
A
DQ
DQ
E
W
A
A
COLUMN I/O
COLUMN DECODER
DQ
DQ
Order this document
by MCM6246/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
WJ PACKAGE
400 MIL SOJ
CASE 893–01
PIN ASSIGNMENT
MCM6246
A
Address Inputs
. . . . . . . . . . . . . . . . . . .
W
Write Enable
. . . . . . . . . . . . . . . . . . . .
G
Output Enable
. . . . . . . . . . . . . . . . . . .
E
Chip Enable
. . . . . . . . . . . . . . . . . . . . . .
DQ
Data Input/Output
. . . . . . . . . . . . . . .
NC
No Connection
. . . . . . . . . . . . . . . . .
VCC
+ 5 V Power Supply
. . . . . . . . . . . .
VSS
Ground
. . . . . . . . . . . . . . . . . . . . . . .
PIN NAMES
5
4
3
2
1
10
9
8
7
6
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
19
27
28
32
31
30
29
36
35
34
33
A
A
A
A
E
A
VSS
VCC
DQ
DQ
DQ
DQ
A
A
W
A
A
A
VCC
DQ
DQ
A
A
A
A
A
NC
VSS
A
A
A
G
DQ
DQ
NC
A
REV 5
6/9/97
©
Motorola, Inc. 1997
MCM6246
2
MOTOROLA FAST SRAM
TRUTH TABLE
(X = Don’t Care)
E
G
W
Mode
I/O Pin
Cycle
Current
H
X
X
Not Selected
High–Z
—
ISB1, ISB2
L
H
H
Output Disabled
High–Z
—
ICCA
L
L
H
Read
Dout
Read
ICCA
L
X
L
Write
High–Z
Write
ICCA
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Symbol
Value
Unit
Power Supply Voltage Relative to VSS
VCC
– 0.5 to + 7.0
V
Voltage Relative to VSS for Any Pin
Except VCC
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
±
20
mA
Power Dissipation
PD
1.0
W
Temperature Under Bias
Tbias
– 10 to + 85
°
C
Ambient Temperature
TA
0 to + 70
°
C
Storage Temperature — Plastic
Tstg
– 55 to + 150
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are ex-
ceeded. Functional operation should be restricted to RECOMMENDED OPERAT-
ING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.2
—
VCC + 0.3**
V
Input Low Voltage
VIL
– 0.5
*
—
0.8
V
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width
≤
2.0 ns).
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width
≤
2.0 ns).
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(I)
—
±
1.0
µ
A
Output Leakage Current (E = VIH, Vout = 0 to VCC)
Ilkg(O)
—
±
1.0
µ
A
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
—
V
POWER SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
AC Active Supply Current (Iout = 0 mA,
MCM6246–17: tAVAV = 17 ns
VCC = max)
MCM6246–20: tAVAV = 20 ns
MCM6246–25: tAVAV = 25 ns
MCM6246–35: tAVAV = 35 ns
ICC
—
—
—
—
—
185
170
155
205
200
185
170
mA
AC Standby Current (VCC = max,
MCM6246–17: tAVAV = 17 ns
E = VIH, No other restrictions on
MCM6246–20: tAVAV = 20 ns
other inputs)
MCM6246–25: tAVAV = 25 ns
MCM6246–35: tAVAV = 35 ns
ISB1
—
—
—
—
55
55
45
35
60
60
50
40
mA
CMOS Standby Current (E
≥
VCC – 0.2 V, Vin
≤
VSS + 0.2 V or
≥
VCC – 0.2 V) (VCC = max, f = 0 MHz)
ISB2
—
10
15
mA
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad-
vised that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high impedance
circuits.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear
feet per minute is maintained.
MCM6246
3
MOTOROLA FAST SRAM
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25
°
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
All Inputs Except Clocks and DQs
E, G, W
Cin
Cck
4
5
6
8
pF
Input/Output Capacitance
DQ
CI/O
5
8
pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
2 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Output Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . .
Output Load
See Figure 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING
(See Note 1)
MCM6246–17
MCM6246–20
MCM6246–25
MCM6246–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
17
—
20
—
25
—
35
—
ns
2, 3
Address Access Time
tAVQV
—
17
—
20
—
25
—
35
ns
Enable Access Time
tELQV
—
17
—
20
—
25
—
35
ns
4
Output Enable Access Time
tGLQV
—
6
—
6
—
8
—
10
ns
Output Hold from Address
Change
tAXQX
5
—
5
—
5
—
5
—
ns
Enable Low to Output Active
tELQX
5
—
5
—
5
—
5
—
ns
5, 6, 7
Output Enable Low to Output
Active
tGLQX
0
—
0
—
0
—
0
—
ns
5, 6, 7
Enable High to Output High–Z
tEHQZ
—
8
—
8
—
10
—
12
ns
5, 6, 7
Output Enable High to Output
High–Z
tGHQZ
—
8
—
8
—
10
—
12
ns
5, 6, 7
Power Up Time
tELICCH
0
—
0
—
0
—
0
—
ns
Power Down Time
tEHICCL
—
17
—
20
—
25
—
35
ns
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus conten-
tion conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low/E going high.
5. At any given voltage and temperature, tEHQZ max
t
tELQX min, and tGHQZ max
t
tGLQX min, both for a given device and from device
to device.
6. Transition is measured
±
500 mV from steady–state voltage.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E
≤
VIL, G
≤
VIL).
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Figure 1. AC Test Load
MCM6246
4
MOTOROLA FAST SRAM
READ CYCLE 1
(See Note 8)
tAXQX
tAVAV
tAVQV
DATA VALID
PREVIOUS DATA VALID
A (ADDRESS)
Q (DATA OUT)
READ CYCLE 2
(See Note)
Q (DATA OUT)
A (ADDRESS)
E (CHIP ENABLE)
G (OUTPUT ENABLE)
NOTE: Addresses valid prior to or coincident with E going low/ E going high.
tAVAV
tELQV
tELQX
tEHQZ
tGHQZ
tGLQV
tGLQX
tAVQV
tELICCH
tEHICCL
ISB
SUPPLY CURRENT
ICC
HIGH–Z
DATA VALID
MCM6246
5
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
MCM6246–17
MCM6246–20
MCM6246–25
MCM6246–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
17
—
20
—
25
—
35
—
ns
4
Address Setup Time
tAVWL
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVWH
14
—
14
—
17
—
20
—
ns
Write Pulse Width
tWLWH,
tWLEH
13
—
13
—
17
—
20
—
ns
Data Valid to End of Write
tDVWH
10
—
10
—
10
—
15
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
0
9
0
9
0
10
0
15
ns
5,6,7
Write High to Output Active
tWHQX
5
—
5
—
5
—
5
—
ns
5,6,7
Write Recovery Time
tWHAX
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus conten-
tion conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
5. Transition is measured
±
500 mV from steady–state voltage.
6. This parameter is sampled and not 100% tested.
7. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
WRITE CYCLE 1
(W Controlled, See Notes 1, 2, and 3)
DATA VALID
HIGH–Z
HIGH–Z
tAVAV
tAVWH
tWHAX
tWHDX
tWHQX
tWLWH
tAVWL
tDVWH
tWLQZ
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tWLEH
MCM6246
6
MOTOROLA FAST SRAM
WRITE CYCLE 2
(E Controlled, See Notes 1, 2, and 3)
MCM6246–17
MCM6246–20
MCM6246–25
MCM6246–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
17
—
20
—
25
—
35
—
ns
4
Address Setup Time
tAVEL
0
—
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVEH
14
—
14
—
17
—
20
—
ns
Enable Pulse Width
tELEH,
tELWH
14
—
14
—
17
—
20
—
ns
5,6
Write Pulse Width
tWLEH
14
—
14
—
17
—
20
—
ns
Data Valid to End of Write
tDVEH
9
—
10
—
10
—
15
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus conten-
tion conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
6. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
(E Controlled, See Notes 1, 2, and 3)
DATA VALID
HIGH–Z
tAVAV
tAVEH
tAVEL
tELWH
tEHAX
tDVEH
tEHDX
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tELEH
tWLEH
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number
Package (WJ = 400 mil SOJ)
Full Part Numbers — MCM6246WJ17
MCM6246WJ17R2
MCM6246WJ20
MCM6246WJ20R2
MCM6246WJ25
MCM6246WJ25R2
MCM6246WJ35
MCM6246WJ35R2
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (17 = 17 ns, 20 = 20 ns, 25 = 25 ns,
35 = 35 ns)
MCM
6246
XX
XX
XX
MCM6246
7
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
400 MIL SOJ
CASE 893–01
0.920
0.395
0.128
0.016
0.088
0.026
0.035
0.030
0.435
0.365
0.030
0.930
0.405
0.148
0.020
0.098
0.032
0.045
0.045
0.445
0.375
0.040
0.050 BASIC
0.025 BASIC
23.37
10.04
3.26
0.41
2.24
0.67
0.89
0.77
11.05
9.28
0.77
23.62
10.28
3.75
0.50
2.48
0.81
1.14
1.14
11.30
9.52
1.01
1.27 BASIC
0.64 BASIC
MILLIMETERS
MIN
MIN
MAX
MAX
INCHES
DIM
A
B
C
D
E
F
G
K
L
N
P
R
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TO BE DETERMINED AT PLANE -T-.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.006 (0.15) PER SIDE.
5. DIMENSION A AND B INCLUDE MOLD MISMATCH
AND ARE DETERMINED AT THE PARTING LINE.
0.004 (0.010)
SEATING
PLANE
-T-
19
36
18
1
F
36 PL
D
36 PL
N
36 PL
A
-X-
DETAIL A
L
2 PL
G
34 PL
K
P
B
-Y-
C
E
R
S RADIUS
36 PL
NOTE 3
DETAIL A
T
0.007 (0.17)
Y
X
M
S
S
T
0.007 (0.17)
Y
X
M
S
S
T
0.007 (0.17)
Y
X
M
S
S
NOTE 3
MCM6246
8
MOTOROLA FAST SRAM
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
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MCM6246/D
◊