MCM63Z736
D
MCM63Z818
1
MOTOROLA FAST SRAM
Advance Information
128K x 36 and 256K x 18 Bit
Pipelined ZBT
™
RAM
Synchronous Fast Static RAM
The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide
zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during
back–to–back read/write and write/read cycles. The MCM63Z736 is organized
as 128K words of 36 bits each and the MCM63Z818 is organized as 256K words
of 18 bits each, fabricated with high performance silicon gate CMOS
technology. This device integrates input registers, an output register, a 2–bit
address counter, and high speed SRAM onto a single monolithic circuit for
reduced parts count in communication applications. Synchronous design
allows precise cycle control with the use of an external clock (CK). CMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQ), and all control signals except output enable
(G) and linear burst order (LBO) are clock (CK) controlled through positive–
edge–triggered noninverting registers.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (CK) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored by an edge–
triggered output register and then released to the output buffers at the next rising
edge of clock (CK).
•
3.3 V LVTTL and LVCMOS Compatible
•
MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)
MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)
•
Selectable Burst Sequencing Order (Linear/Interleaved)
•
Internally Self–Timed Write Cycle
•
Two–Cycle Deselect
•
Byte Write Control
•
ADV Controlled Burst
•
100–Pin TQFP Package
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM63Z736/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM63Z736
MCM63Z818
TQ PACKAGE
TQFP
CASE 983A–01
REV 1
2/6/98
©
Motorola, Inc. 1998
MCM63Z736
D
MCM63Z818
2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
71
72
DQc
VDDQ
DQb
69
70
66
67
68
64
65
61
62
63
3738
34 35 36
42 43
39 40 41
4546
44
60
59
58
57
56
55
54
53
52
51
31 32 33
74
75
76
77
78
79
80
50
49
48
47
DQb
DQb
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VDDQ
VSS
VSS
VDDQ
DQc
DQc
DQc
DQc
DQc
DQc
DQc
SA
SA
SE1
SBd
CK
SBc
NC
G
SA0
SA
SA
SA
SA
NC
NC
NC
LBO
SA1
V DD
VDD
DQa
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
VDDQ
DQa
DQa
DQd
VDD
VSS
VSS
VDDQ
DQd
DQd
DQd
DQd
DQd
73
DQc
94 93
97 9695
89 88
92 91 90
86 85
87
100 99 98
81
82
83
84
10
9
12
11
15
14
13
17
16
20
19
18
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
8
SA
SA
CKE
SE2
SE3
V SS
V DD
VDDQ
VSS
DQd
DQd
DQd
SA
SA
SA
SA
SA
SA
SA
NC
V SS
NC
ADV
SW
SBa
SBb
VDD
VDD
VSS
VDD
TOP VIEW
MCM63Z736
MCM63Z736
D
MCM63Z818
3
MOTOROLA FAST SRAM
PIN ASSIGNMENT
71
72
NC
VDDQ
SA
69
70
66
67
68
64
65
61
62
63
3738
34 35 36
42 43
39 40 41
4546
44
60
59
58
57
56
55
54
53
52
51
31 32 33
74
75
76
77
78
79
80
50
49
48
47
NC
NC
VSS
DQa
NC
DQa
DQa
VSS
VDDQ
DQa
DQa
VDDQ
VSS
VSS
VDDQ
NC
NC
NC
DQb
DQb
DQb
DQb
SA
SA
SE1
NC
CK
NC
NC
G
SA0
SA
SA
SA
SA
NC
NC
NC
SA1
V DD
VDD
DQa
VSS
DQa
DQa
NC
DQa
VSS
VDDQ
NC
NC
VSS
VDDQ
NC
NC
DQb
VDD
VSS
VSS
VDDQ
DQb
DQb
DQb
DQb
NC
73
NC
94 93
97 9695
89 88
92 91 90
86 85
87
100 99 98
81
82
83
84
10
9
12
11
15
14
13
17
16
20
19
18
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
8
SA
SA
CKE
SE2
SE3
V SS
V DD
VDDQ
VSS
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
NC
V SS
NC
ADV
SW
SBa
SBb
VDD
VDD
VSS
VDD
TOP VIEW
MCM63Z818
LBO
MCM63Z736
D
MCM63Z818
4
MOTOROLA FAST SRAM
MCM63Z736 PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
87
CKE
Input
Clock Enable: Disables the CK input when CKE is high.
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
DQx
I/O
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b, c, d).
86
G
Input
Asynchronous Output Enable.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low – linear burst counter.
High – interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA0, SA1
Input
Synchronous Burst Address Inputs: The two LSB’s of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b, c, d) in conjunction with SW. Has no effect on read cycles.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
14, 15, 16, 41, 65, 66, 91
VDD
Supply
Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
Supply
I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 64, 67, 71, 76, 90
VSS
Supply
Ground.
38, 39, 42, 43, 83, 84
NC
—
No Connection: There is no connection to the chip.
MCM63Z736
D
MCM63Z818
5
MOTOROLA FAST SRAM
MCM63Z818 PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADV
Input
Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
89
CK
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
87
CKE
Input
Clock Enable: Disables the CK input when CKE is high.
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
DQx
I/O
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
86
G
Input
Asynchronous Output Enable.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low – linear burst counter.
High – interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 80, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA0, SA1
Input
Synchronous Burst Address Inputs: The two LSB’s of the address field.
These pins must preset the burst address counter values. These inputs
are registered and must meet setup and hold times.
93, 94
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: Enables write to byte “x”
(byte a, b) in conjunction with SW. Has no effect on read cycles.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
14, 15, 16, 41, 65, 66, 91
VDD
Supply
Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
Supply
I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 64, 67, 71, 76, 90
VSS
Supply
Ground.
1, 2, 3, 6, 7, 25, 28, 29, 30,
38, 39, 42, 43, 51, 52, 53, 56, 57,
75, 78, 79, 83, 84, 95, 96
NC
—
No Connection: There is no connection to the chip.
MCM63Z736
D
MCM63Z818
6
MOTOROLA FAST SRAM
TRUTH TABLE
CK
CKE
E
SW
SBx
ADV
SA0 –
SAx
Next Operation
Input Command
Code
Notes
L–H
1
X
X
X
X
X
Hold
H
1, 2
L–H
0
False
X
X
0
X
Deselect
D
1, 2
L–H
0
True
0
V
0
V
Load Address, New Write
W
1, 2, 3,
4, 5
L–H
0
True
1
X
0
V
Load Address, New Read
R
1, 2
L–H
0
X
X
V (W)
1
X
Burst
B
1, 2, 4,
6 7
X (R, D)
Continue
6, 7
NOTES:
1. X = don‘t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics.
2. E = true if SE1 and SE3 = 0, and SE2 = 1.
3. Byte write enables, SBx are evaluated only as new write addresses are loaded.
4. No control inputs except CKE, SBx, and ADV are recognized in a clock cycle where ADV is sampled high.
5. A write with SBx not valid does load addresses.
6. A burst write with SBx not valid does increment address.
7. ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous
cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deslect cycle.
WRITE TRUTH TABLE
Cycle Type
SW
SBa
SBb
SBc
(See Note 1)
SBd
(See Note 1)
Read
H
X
X
X
X
Write Byte a
L
L
H
H
H
Write Byte b
L
H
L
H
H
Write Byte c (See Note 1)
L
H
H
L
H
Write Byte d (See Note 1)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
NOTE:
1. Valid only for MCM63Z736.
LINEAR BURST ADDRESS TABLE
(LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE
(LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
MCM63Z736
D
MCM63Z818
7
MOTOROLA FAST SRAM
INPUT COMMAND CODE AND STATE NAME DEFINITION DIAGRAM
FALSE
E
CK
CKE
TRUE
TRUE
SA0 – SAx
VALID
VALID
SW
ADV
VALID
VALID
SBX
D
B
W
B
R
B
H
DESELECT
CONTINUE
DESELECT
NEW WRITE
BURST
WRITE
NEW READ
BURST
READ
HOLD
INPUT
COMMAND
CODE
NOTE: Cycles are named for their control inputs, not for data I/O state.
MCM63Z736
D
MCM63Z818
8
MOTOROLA FAST SRAM
Figure 1. ZBT RAM State Diagram
DESELECT
BURST
WRITE
BURST
READ
W
R
D
NEW
WRITE
NEW
READ
B
W
R
W
R
W
B
B
B
R
B
R
D
D
W
D
D
CURRENT
STATE (n)
NEXT
STATE (n + 1)
TRANSITION
ƒ
INPUT
COMMAND
CODE
KEY:
NOTES:
1. Input command codes (D, W, R, and B) represent control pin inputs
as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state change.
CK
COMMAND
CODE
STATE
ƒ
DQ
n
n + 1
n + 2
n + 3
CURRENT
STATE
NEXT
STATE
Figure 2. State Definitions for ZBT RAM State Diagram
MCM63Z736
D
MCM63Z818
9
MOTOROLA FAST SRAM
Figure 3. Data I/O State Diagram
HIGH–Z
HIGH–Z
(DATA IN)
DATA OUT
(Q VALID)
W
R
B
W
CURRENT
STATE (n)
NEXT STATE
(n + 2)
TRANSITION
ƒ
INPUT
COMMAND
CODE
KEY:
INTERMEDIATE
INTERMEDIATE
INTERMEDIATE
INTERMEDIATE
INTERMEDIATE
B
R
D
D
W
R
INTERMEDIATE
D
B
NOTES:
1. Input command codes (D, W, R, and B) represent control pin
inputs as indicated in the Truth Table.
2. Hold (i.e., CKE sampled high) is not shown simply because
CKE = 1 blocks clock input and therefore, blocks any state
change.
INTERMEDIATE
STATE (n + 1)
TRANSITION
CK
COMMAND
CODE
STATE
STATE NAME
ƒ
DQ
n
n + 1
n + 2
n + 3
CURRENT
STATE
INTERMEDIATE
STATE
NEXT
STATE
Figure 4. State Definitions for I/O State Diagrams
MCM63Z736
D
MCM63Z818
10
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(See Note 1)
Rating
Symbol
Value
Unit
Notes
Power Supply Voltage
VDD
– 0.5 to + 4.6
V
I/O Supply Voltage
VDDQ
VSS – 0.5 to VDD
V
2
Input Voltage Relative to VSS for
Any Pin Except VDD
Vin, Vout
– 0.5 to VDD + 0.5
V
2
Input Voltage (Three State I/O)
VIT
VSS – 0.5 to
VDDQ + 0.5
V
2
Output Current (per I/O)
Iout
±
20
mA
Package Power Dissipation
PD
1.3
W
3
Temperature Under Bias
Tbias
– 10 to 85
°
C
Storage Temperature
Tstg
– 55 to 125
°
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
Symbol
Max
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
R
θ
JA
40
25
°
C/W
1, 2
Junction to Board (Bottom)
R
θ
JB
17
°
C/W
3
Junction to Case (Top)
R
θ
JC
9
°
C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883
Method 1012.1).
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
MCM63Z736
D
MCM63Z818
11
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
5%, TA = 0 to 70
°
C Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDD
3.135
3.3
3.465
V
I/O Supply Voltage
VDDQ*
3.135
3.3
VDD
V
Input Low Voltage
VIL
– 0.3
—
0.8
V
Input High Voltage
VIH
2
—
VDD + 0.3
V
Input High Voltage I/O Pins
VIH2
2
—
VDDQ + 0.3
V
* VDD and VDDQ are shorted together on the device and must be supplied with identical voltage levels.
VIH
20% tKHKH (MIN)
VSS
VSS – 1.0 V
Figure 5. Undershoot Voltage
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V
≤
Vin
≤
VDD)
Ilkg(I)
—
—
±
1
µ
A
1
Output Leakage Current (0 V
≤
Vin
≤
VDDQ)
Ilkg(O)
—
—
±
1
µ
A
AC Supply Current (Device Selected, All Outputs Open,
Freq = Max) Includes Supply Current for Both VDD and VDDQ
IDDA
—
—
350
mA
2, 3, 4
CMOS Standby Supply Current (Device Deselected,
Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS
Levels)
ISB2
—
—
5
mA
5, 6
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)
ISB3
—
—
25
mA
5, 7
Hold Supply Current (Device Selected, Freq = Max,