MCM69D536
1
MOTOROLA FAST SRAM
32K x 36 Bit Synchronous
Dual I/O, Dual Address SRAM
The MCM69D536 is a 1M–bit static random access memory, organized as 32K
words of 36 bits. It features common data input and data output buffers and
incorporates input and output registers on–board with high speed SRAM.
The MCM69D536 allows the user to concurrently perform reads, writes, or
pass–through cycles in combination on the two data ports. The two address ports
(AX, AY) determine the read or write locations for their respective data ports
(DQX, DQY).
The synchronous design allows for precise cycle control with the use of an
external single clock (K). All signal pins except output enables (GX, GY) are
registered on the rising edge of clock (K).
The pass–through feature allows data to be passed from one port to the other,
in either direction. The PTX input must be asserted to pass data from port X to
port Y. The PTY will likewise pass data from port Y to port X. A pass–through
operation takes precedence over a read operation.
For the case when AX and AY are the same, certain protocols are followed. If
both ports are read, the reads occur normally. If one port is written and the other
is read, the read from the array will occur before the data is written. If both ports
are written, only the data on DQY will be written to the array.
•
Single 3.3 V
±
5% Power Supply
•
Fast Access Times: 6/8 ns Max
•
Throughput of 2.98 Gigabits/Second
•
Single Clock Operation
•
Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output
Registers On–Chip
•
83 MHz Maximum Clock Frequency
•
Self–Timed Write
•
Two Bi–Directional Data Buses
•
Can be Configured as Separate I/O
•
Pass–Through Feature
•
Asynchronous Output Enables (GX, GY)
•
LVTTL Compatible I/O
•
Concurrent Reads and Writes
•
176–Pin TQFP Package
Suggested Applications
— ATM
— Ethernet Switches
— Routers
— Cell/Frame Buffers
— SNA Switches
— Shared Memory
Product Family Configurations
Part
Number
Dual
Address
Single
Address
Dual
I/O
Separate
I/O
Configuration
VDD
MCM69D536
n
Note 1
n
Note 2
32K x 36
3.3 V
MCM69D618
n
Note 1
n
Note 2
64K x 18
3.3 V
MCM67Q709A
n
n
128K x 9
5.0 V
MCM67Q909
n
n
512K x 9
5.0 V
NOTES:
1. Tie AX and AY address ports together for the part to function as a single address part.
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.
Order this document
by MCM69D536/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM69D536
TQ PACKAGE
176 LEAD TQFP
CASE 1101–01
REV 4
1/16/98
©
Motorola, Inc. 1998
MCM69D536
2
MOTOROLA FAST SRAM
AX
E1
WX
BLOCK DIAGRAM
PTX
ADDRESS
REGISTER
32K x 36 ARRAY
GX
E2
ADDRESS
REGISTER
15
WRITE X
REGISTER
PTX
REGISTER
PASS–THROUGH
DQX
AY
WRITE
DRIVER
SENSE
AMPS
SENSE
AMPS
WRITE
DRIVER
WRITE Y
REGISTER
WY
PTY
REGISTER
PTY
DATA IN
REGISTER
OUTPUT
REGISTER
OUTPUT
REGISTER
DATA IN
REGISTER
ENABLE
REG 1
GY
DQY
15
ENABLE
REG 2
K
K
MCM69D536
3
MOTOROLA FAST SRAM
PIN ASSIGNMENT
DQX20
51 52
48 49 50
56 57
53 54 55
59 60
58
45 46 47
64
63
62
61
VDD
VSS
VDD
VSS
DQY20
DQX21
DQY21
DQX22
DQY22
DQX23
DQY23
DQX24
DQX35
DQY34
DQX34
V
SSi
DQY35
DQX25
DQY24
VSS
DQY28
DQX28
DQY25
VDD
VSS
DQY27
DQX27
VSSi
10
9
12
11
15
14
13
17
16
20
19
18
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
8
VDD
DQX26
DQY26
VDD
VSS
DQY29
71 72
69
68
70
76 77
73 74 75
79 80
78
65 66 67
84
83
82
81
DQY0
NC
NC
NC
DQX0
NC
88
87
86
85
DQY1
DQX1
DQY30
VDD
VSS
VDD
VSS
DQX30
DQY31
DQX31
DQY32
DQX32
DQY33
DQX33
VSSi
DQX29
40
39
42
41
44
43
37
36
35
34
33
32
31
38
DQX2
VDD
VSS
VDD
VSS
DQY2
DQX3
DQY3
DQX4
DQY4
DQX5
DQY5
DQX6
DQX17
DQY16
DQX16
NC
NC
DQY17
DQX7
DQY6
VSS
DQY10
DQX10
DQY7
VDD
VSS
DQY9
DQX9
VSSi
98
97
100
99
103
102
101
105
104
108
107
106
109
110
111
112
113
114
115
116
117
118
95
94
93
92
91
89
90
96
VDD
DQX8
DQY8
VDD
VSS
DQY11
E2
GX
PTY
WX
WY
E1
PTX
NC
K
NC
NC
NC
NC
GY
NC
DQY18
AX7
AY
6
AX6
DQX18
AY
7
DQY19
DQX19
DQY12
VDD
VSS
VDD
VSS
DQX12
DQY13
DQX13
DQY14
DQX14
DQY15
DQX15
VSSi
DQX11
128
127
130
129
132
131
125
124
123
122
121
120
119
126
170
175
174
173
172
168
169
165
164
167
176
171
166
158
157
162
161
160
159
163
150
155
154
153
152
148
149
145
144
147
156
151
138
137
142
141
140
139
143
134
133
136
135
146
V
SSi
V
SS
V
DD
V
SSi
AY
5
AX5
AY
4
AX4
AY
3
AX3
AY
2
AX2
AY
1
AX1
AY
0
AX0
V
SS
V
DD
AX10
A
Y10
AX1
1
AY
11
AX12
A
Y12
AX13
A
Y13
AX14
A
Y14
V
DD
V
SS
V
SSi
V
SSi
V
DD
V
SS
AX9
AY
9
AX8
AY
8
V
DD
V
SS
NC
NC
V
SSi
V
SS
V
SSi
V
DD
MCM69D536
4
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
65, 63, 61, 59, 57, 55, 169, 167,
145, 143, 68, 70, 72, 74, 76
AX0 –
AX14
Input
Address Port X. Never allow floating addresses for inputs AX0 – AX14.
A pullup resistor is needed.
64, 62, 60, 58, 56, 54, 168, 166,
144, 142, 69, 71, 73, 75, 77
AY0 –
AY14
Input
Address Port Y. Never allow floating addresses for inputs AY0 – AY14.
A pullup resistor is needed.
82, 86, 90, 94, 96, 100, 102, 106, 108,
113. 115, 119, 121, 125, 127, 131,
135, 139, 170, 174, 2, 6, 8, 12, 14, 18,
20, 25, 27, 31, 33, 37, 39, 43, 47, 51
DQX0 –
DQX35
I/O
Data Input/Output Port X.
83, 87, 91, 95, 97, 101, 103, 107, 109,
112, 114, 118, 120, 124, 126, 130, 134,
138, 171, 175, 3, 7, 9, 13, 15, 19, 21,
24, 26, 30, 32, 36, 38, 42, 46, 50
DQY0 –
DQY35
I/O
Data Input/Output Port Y.
150
E1
Input
Synchronous Chip Enable: Active low.
151
E2
Input
Synchronous Chip Enable: Active high.
152
GX
Input
Asynchronous Output Enable Port X Input:
Low — enables output buffers (DQXx pins).
High — DQXx pins are high impedance.
153
GY
Input
Asynchronous Output Enable Port Y Input:
Low — enables output buffers (DQYx pins).
High — DQYx pins are high impedance.
156
K
Input
Clock: This signal registers the address, data in, and all control signals
except G.
146
PTX
Input
Pass–Through Port X.
147
PTY
Input
Pass–Through Port Y.
148
WX
Input
Synchronous Write Enable Port X.
149
WY
Input
Synchronous Write Enable Port Y.
4, 10, 16, 22, 28, 34, 40, 49,
67, 84, 92, 98, 104, 110,
116, 122, 128, 137, 155, 172
VDD
Supply
+ 3.3 V Power Supply.
5, 11, 17, 23, 29, 35, 41, 48,
66, 85, 93, 99, 105, 111,
117, 123. 129, 136, 154, 173
VSS
Supply
Ground.
1, 44, 45, 52, 53, 88,
89, 132, 133, 165, 176
VSSi
Input
Bonded to die flag. No chip current flows through these pins.
78– 81, 140, 141, 157 – 164
NC
—
No Connection: There is no connection to the chip.
MCM69D536
5
MOTOROLA FAST SRAM
TRUTH TABLE
(See Notes 1 through 5)
O
i
N
b
Input at tn Clock
Operation Number
E1
E2
WX
WY
PTX
PTY
Operation
1
H
X
X
X
X
X
Deselected
2
X
L
X
X
X
X
Deselected
3
L
H
0
X
X
X
Write X Port
4
L
H
X
0
X
X
Write Y Port
5
L
H
X
X
0
X
Pass–Through X to Y
6
L
H
X
X
X
0
Pass–Through Y to X
7
L
H
1
X
1
1
Read X
8
L
H
X
1
1
1
Read Y
NOTES:
1. GX/GY must be controlled to avoid bus contention issues during write and pass–through cycles.
2. Operation numbers 3 – 6 can be used in any combination.
3. Operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined.
4. Operation number 5 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.
5. Operation number 6 can not be combined with operation number 7 or 8 because pass–through takes precedence over a read operation.
K
ADDRESS & CONTROL
VALID
tn
tn + 1
VALID
DATA INPUT D
VALID
DATA OUTPUT Q
PIPELINED READ ACCESS
PASS–THROUGH
ABSOLUTE MAXIMUM RATINGS
(See Note)
Rating
Symbol
Value
Unit
Power Supply Voltage
VDD
– 0.5 to + 4.6
V
Voltage Relative to VSS for Any Pin
Except VDD
Vin, Vout
– 0.5 to VDD + 0.5
V
Output Current
Iout
±
20
mA
Power Dissipation
PD
TBD
W
Temperature Under Bias
Tbias
– 10 to + 85
°
C
Operating Temperature
TA
0 to + 70
°
C
Storage Temperature — Plastic
Tstg
– 55 to + 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This is a synchronous device. All synchro-
nous inputs must meet specified setup and hold
times with stable logic levels for
ALL rising
edges of clock (K) while the device is selected.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
MCM69D536
6
MOTOROLA FAST SRAM
PACKAGE THERMAL CHARACTERISTICS
(See Note 1)
Rating
Symbol
TQFP
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single–Layer Board
Four–Layer Board
R
θ
JA
40
35
°
C/W
2
Junction to Board (Bottom)
R
θ
JB
23
°
C/W
3
Junction to Case (Top)
R
θ
JC
9
°
C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
5%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
VDD
3.135
3.465
V
Input High Voltage
VIH
2.0
VDD + 0.5**
V
Input Low Voltage
VIL
– 0.5*
0.8
V
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Ilkg(I)
—
±
1.0
µ
A
Output Leakage Current (E = VIH, Vout = 0 to VDD)
Ilkg(O)
—
±
1.0
µ
A
AC Supply Current (Iout = 0 mA) (VDD = max, f = fmax)
MCM69D536–6 ns
MCM69D536–8 ns
IDDA
—
—
300
300
mA
CMOS Standby Supply Current (Deselected, Clock (K)
MCM69D536–6 ns
Cycle Time
≥
tKHKH, All Inputs Toggling at CMOS Levels MCM69D536–8 ns
Vin
≤
VSS + 0.2 V or
≥
VDD – 0.2 V)
ISB1
—
—
100
100
mA
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
VDD
V
* VIL
≥
– 1.5 V for t
≤
tKHKH/2.
** VIH
≤
VDD + 1.0 V for t
≤
tKHKH/2.
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70
°
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Max
Unit
Address and Data Input Capacitance
Cin
6
pF
Control Pin Input Capacitance
Cin
6
pF
Output Capacitance
Cout
8
pF
MCM69D536
7
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
5%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
3 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
Figure 1 Unless Otherwise Noted
. . . . . . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING
(See Notes 1, 2, and 3)
MCM69D536–6
MCM69D536–8
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
12
—
15
—
ns
1
Clock Access Time
tKHQV
—
6
—
8
ns
Clock Low Pulse Width
tKLKH
4
—
6
—
ns
Clock High Pulse Width
tKHKL
4
—
6
—
ns
Clock High to Data Output Active
tKHQX1
0
—
0
—
ns
Clock High to Data Output Invalid
tKHQX2
2
—
2
—
ns
Clock High to Data Output High–Z
tKHQZ
—
5
—
5
ns
2
Output Enable Low to Data Output Valid
tGLQV
—
6
—
8
ns
Output Enable Low to Data Output Low–Z
tGLQX
0
—
0
—
ns
Output Enable High to Data Output High–Z
tGHQZ
—
5
—
8
ns
2
Setup Times:
AWR0 – AWR14
ARD0 – ARD14
W
PT
E1, E2
D0 – D35
tAVKH
tAVKH
tWVKH
tPTVKH
tEVKH
tDVKH
2.5
—
3
—
ns
3
Hold Times:
AWR0 – AWR14
ARD0 – ARD14
W
PT
E1, E2
D0 – D35
tKHAX
tKHAX
tKHWX
tKHPTX
tKHEX
tKHDX
0.5
—
1
—
ns
3
3
3
3
3
3, 4
NOTES:
1. All read and write cycles are referenced from K.
2. This parameter is sampled and not 100% tested.
3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for
ALL rising
edges of clock (K) while the device is selected.
4. tKHDX minimum for Port Y only extends to 4.0 ns only for the special case when the Y– and X–address are identical on the same rising
clock edge.
OUTPUT
Z0 = 50
Ω
RL = 50
Ω
VL = 1.5 V
Figure 1. AC Test Load
MCM69D536
8
MOTOROLA FAST SRAM
1
K
AX
E
tKHKH
tKLKH
tKHKL
2
3
4
5
6
7
8
9
GX
DQX
tGLQV
tGHQZ
tKHQV
tKHQX1
Q(1)
Q(2)
Q(3)
Q(5)
Q(6)
12
AY
13
14
15
16
6
7
19
20
GY
DQY
tKHQZ
Q(12)
Q(13)
Q(14)
Q(16)
Q(6)
Q(7)
Q(7)
tGLQX
tEVKH
tKHEX
tKHQV
PORT X
PORT Y
NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low.
tAVKH
tKHAX
READ CYCLE TIMING FROM BOTH PORTS (WX, WY, PTX, PTY HIGH)
MCM69D536
9
MOTOROLA FAST SRAM
K
AX
E
tKHKH
tKLKH
tKHKL
GX
DQX
AY
GY
D(2)
D(3)
D(4)
D(5)
D(6)
D(8)
D(9)
tKHWX
PORT X
WX
PORT Y
WY
DQY
D(14)
D(15)
D(19)
D(18)
tWVKH
tKHDX
tDVKH
NOTE: E Low = E1 Low and E2 High. E High = E1 High or E2 Low.
PORT Y TAKES PRECEDENCE
OVER PORT X WHEN AX = AY
AND WRITING BOTH PORTS.
WRITE CYCLE TIMING TO BOTH PORTS (PTX, PTY HIGH)
1
2
3
4
5
6
7
8
9
12
13
14
15
5
6
18
19
20
MCM69D536
10