MCM69P819
1
MOTOROLA FAST SRAM
256K x 18 Bit Pipelined
BurstRAM Synchronous
Fast Static RAM
The MCM69P819 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC
™
and other
high performance microprocessors. It is organized as 256K words of 18 bits
each. This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and linear burst order (LBO) are clock (K) controlled through positive–
edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69P819 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and
SBb controls DQb. Individual bytes are written if the selected byte writes SBx are
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and
SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM69P819 operates from a 3.3 V core power supply and all outputs
operate on a 2.5 or 3.3 V power supply. All inputs and outputs are JEDEC stan-
dard JESD8–5 compatible.
•
MCM69P819–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)
MCM69P819–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)
MCM69P819–4: 4 ns Access/7.5 ns Cycle (133 MHz)
•
3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply
•
ADSP, ADSC, and ADV Burst Control Pins
•
Selectable Burst Sequencing Order (Linear/Interleaved)
•
Single–Cycle Deselect Timing
•
Internally Self–Timed Write Cycle
•
Byte Write and Global Write Control
•
PB1 Version 2.0 Compatible
•
JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Order this document
by MCM69P819/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM69P819
ZP PACKAGE
PBGA
CASE 999–02
TQ PACKAGE
TQFP
CASE 983A–01
REV 6
1/20/98
©
Motorola, Inc. 1998
MCM69P819
2
MOTOROLA FAST SRAM
WRITE
REGISTER
a
ENABLE
REGISTER
BURST
COUNTER
ADSP
G
CLR
WRITE
REGISTER
b
SBa
SBb
SE3
16
18
SGW
DATA–OUT
REGISTER
ENABLE
REGISTER
K2
K
ADDRESS
REGISTER
18
DATA–IN
REGISTER
256K x 18 ARRAY
SE2
LBO
ADV
K
ADSC
SA
SA1
SA0
SW
SE1
K
2
18
2
2
K2
DQa – DQb
18
FUNCTIONAL BLOCK DIAGRAM
MCM69P819
3
MOTOROLA FAST SRAM
TOP VIEW 119 BUMP PBGA
6
5
4
3
2
1
7
B
C
VSS
G
A
D
E
F
H
J
VSS
VSS
VSS
VSS
SA
VSS
VSS
VSS
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
NC
NC
NC
SA
SA
NC
NC
SW
NC
NC
VDDQ
VDDQ
NC
VDDQ
DQa
DQa
DQa
DQa
NC
VDD
NC
NC
NC
NC
NC
NC
NC
DQb
VSS
SA0
NC
LBO
NC
DQa
SA1
VSS
NC
DQb
VDDQ DQb VSS
NC
NC
DQa
SBa
VSS
NC
DQb
NC
DQb
VSS
K
VSS
DQb
NC
VDD
NC
VDD
NC
VDD
VDDQ
NC
VSS SGW
DQa
DQa
NC
ADV
SBb
DQb
NC
VDDQ
NC
VSS
G
NC
SE1
VSS
DQb
NC
DQb
NC
VSS
NC
DQa
VDD
NC
NC
SE2
SA
ADSC
ADSP
K
L
M
N
P
R
T
U
Not to Scale
VDDQ
VDDQ
SE3
VDDQ
VDDQ
NC
71
72
NC
VDDQ
SA
69
70
66
67
68
64
65
61
62
63
3738
34 35 36
42 43
39 40 41
4546
44
60
59
58
57
56
55
54
53
52
51
31 32 33
74
75
76
77
78
79
80
50
49
48
47
NC
NC
VSS
DQa
NC
DQa
DQa
VSS
VDDQ
DQa
DQa
VDDQ
VSS
VSS
VDDQ
NC
NC
NC
DQb
DQb
DQb
DQb
NC
SA
SA
SE1
NC
K
NC
ADV
G
SA0
SA
SA
SA
SA
NC
NC
NC
LBO
SA1
V DD
VDD
NC
DQa
VSS
DQa
DQa
NC
DQa
VSS
VDDQ
NC
NC
VDDQ
NC
NC
DQb
VDD
VSS
VSS
VDDQ
DQb
DQb
DQb
DQb
NC
73
NC
94 93
97 9695
89 88
92 91 90
86 85
87
100 99 98
81
82
83
84
10
9
12
11
15
14
13
17
16
20
19
18
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
8
SA
SA
SW
SE2
SE3
V SS
V DD
NC
NC
VDDQ
VSS
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
TOP VIEW 100 PIN TQFP
NC
V SS
ADSP
ADSC
SGW
SBa
SBb
PIN ASSIGNMENTS
VSS
MCM69P819
4
MOTOROLA FAST SRAM
PBGA PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
4B
ADSC
Input
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
4A
ADSP
Input
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
4G
ADV
Input
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
I/O
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
4F
G
Input
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
4K
K
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
3R
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
4N, 4P
SA1, SA0
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
5L, 3G
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
4E
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
2B
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
6B
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
4H
SGW
Input
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
4M
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
4C, 2J, 4J, 6J, 4R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
I/O Power Supply.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P
VSS
Supply
Ground.
1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,
2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K,
2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,
5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U
NC
—
No Connection: There is no connection to the chip.
MCM69P819
5
MOTOROLA FAST SRAM
TQFP PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
85
ADSC
Input
Synchronous Address Status Controller: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.
84
ADSP
Input
Synchronous Address Status Processor: Active low, interrupts any
ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP is asserted and SE1 is high).
83
ADV
Input
Synchronous Address Advance: Increments address count in
accordance with counter type selected (linear/interleaved).
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24
DQx
I/O
Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
86
G
Input
Asynchronous Output Enable Input:
Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.
89
K
Input
Clock: This signal registers the address, data in, and all control signals
except G and LBO.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,
80, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1, SA0
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94
(a) (b)
SBx
Input
Synchronous Byte Write Inputs: “x” refers to the byte being written (byte
a, b). SGW overrides SBx.
98
SE1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Input
Synchronous Chip Enable: Active low for depth expansion.
88
SGW
Input
Synchronous Global Write: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87
SW
Input
Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins. If only byte write signals SBx
are being used, tie this pin low.
15, 41, 65, 91
VDD
Supply
Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
Supply
I/O Power Supply.
5, 10, 17, 21, 26, 40,
55, 60, 67, 71, 76, 90
VSS
Supply
Ground.
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,
39, 42, 43, 51, 52, 53, 56, 57, 64, 66, 75,
78, 79, 95, 96
NC
—
No Connection: There is no connection to the chip.
MCM69P819
6
MOTOROLA FAST SRAM
TRUTH TABLE
(See Notes 1 Through 5)
Next Cycle
Address
Used
SE1
SE2
SE3
ADSP
ADSC
ADV
G 3
DQx
Write 2, 4
Deselect
None
1
X
X
X
0
X
X
High–Z
X
Deselect
None
0
X
1
0
X
X
X
High–Z
X
Deselect
None
0
0
X
0
X
X
X
High–Z
X
Deselect
None
X
X
1
1
0
X
X
High–Z
X
Deselect
None
X
0
X
1
0
X
X
High–Z
X
Begin Read
External
0
1
0
0
X
X
X
High–Z
X5
Begin Read
External
0
1
0
1
0
X
X
High–Z
READ5
Continue Read
Next
X
X
X
1
1
0
1
High–Z
READ
Continue Read
Next
X
X
X
1
1
0
0
DQ
READ
Continue Read
Next
1
X
X
X
1
0
1
High–Z
READ
Continue Read
Next
1
X
X
X
1
0
0
DQ
READ
Suspend Read
Current
X
X
X
1
1
1
1
High–Z
READ
Suspend Read
Current
X
X
X
1
1
1
0
DQ
READ
Suspend Read
Current
1
X
X
X
1
1
1
High–Z
READ
Suspend Read
Current
1
X
X
X
1
1
0
DQ
READ
Begin Write
External
0
1
0
1
0
X
X
High–Z
WRITE
Continue Write
Next
X
X
X
1
1
0
X
High–Z
WRITE
Continue Write
Next
1
X
X
X
1
0
X
High–Z
WRITE
Suspend Write
Current
X
X
X
1
1
1
X
High–Z
WRITE
Suspend Write
Current
1
X
X
X
1
1
X
High–Z
WRITE
NOTES:
1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must
also remain negated at the completion of the write cycle to ensure proper write data hold times.
5. This read assumes the RAM was previously deselected.
LINEAR BURST ADDRESS TABLE
(LBO = VSS)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . . X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE
(LBO = VDD)
1st Address (External)
2nd Address (Internal)
3rd Address (Internal)
4th Address (Internal)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X00
X . . . X11
X . . . X10
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
SGW
SW
SBa
SBb
Read
H
H
X
X
Read
H
L
H
H
Write Byte a
H
L
L
H
Write Byte b
H
L
H
L
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X
MCM69P819
7
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(See Note 1)
Rating
Symbol
Value
Unit
Notes
Power Supply Voltage
VDD
VSS – 0.5 to + 4.6
V
I/O Supply Voltage
VDDQ
VSS – 0.5 to VDD
V
2
Input Voltage Relative to VSS for
Any Pin Except VDD
Vin, Vout
VSS – 0.5 to
VDD + 0.5
V
2
Input Voltage (Three–State I/O)
VIT
VSS – 0.5 to
VDDQ + 0.5
V
2
Output Current (per I/O)
Iout
±
20
mA
Package Power Dissipation
PD
1.6
W
3
Ambient Temperature
TA
0 to 70
°
C
Die Temperature
TJ
110
°
C
3
Temperature Under Bias
Tbias
– 10 to 85
°
C
Storage Temperature
Tstg
– 55 to 125
°
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. This is a steady–state DC parameter that is in effect after the power supply has
achieved its nominal operating level. Power sequencing is not necessary.
3. Power dissipation capability is dependent upon package characteristics and use
environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS — PBGA
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single Layer Board
Four Layer Board
R
θ
JA
38
22
°
C/W
1, 2
Junction to Board (Bottom)
R
θ
JB
14
°
C/W
3
Junction to Case (Top)
R
θ
JC
5
°
C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
PACKAGE THERMAL CHARACTERISTICS — TQFP
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (@ 200 lfm)
Single Layer Board
Four Layer Board
R
θ
JA
40
25
°
C/W
1, 2
Junction to Board (Bottom)
R
θ
JB
17
°
C/W
3
Junction to Case (Top)
R
θ
JC
9
°
C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, board population, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC–883 Method 1012.1).
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
MCM69P819
8
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply
(Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDD
3.135
3.3
3.6
V
I/O Supply Voltage
VDDQ
2.375
2.5
2.9
V
Input Low Voltage
VIL
– 0.3
—
0.7
V
Input High Voltage
VIH
1.7
—
VDD + 0.3
V
Input High Voltage (I/O Pins)
VIH2
1.7
—
VDDQ + 0.3
V