MCM69R736A
•
MCM69R818A
1
MOTOROLA FAST SRAM
Advance Information
4M Late Write HSTL
The MCM69R736A/818A is a 4 megabit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R818A
organized as 256K words by 18 bits, and the MCM69R736A organized as 128K
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential CK clock inputs control the timing of read/write operations of
the RAM. At the rising edge of the CK clock all addresses, write enables, and
synchronous selects are registered. An internal buffer and special logic enable
the memory to accept write data on the rising edge of the CK clock a cycle after
address and control signals. Read data is driven on the rising edge of the CK
clock also.
The RAM uses HSTL inputs and outputs. The adjustable input trip – point (Vref)
and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
•
Byte Write Control
•
Single 3.3 V +10%, – 5% Operation
•
HSTL – I/O (JEDEC Standard JESD8–6 Class I Compatible)
•
HSTL – User Selectable Input Trip–Point
•
HSTL – Compatible Programmable Impedance Output Drivers
•
Register to Register Synchronous Operation
•
Asynchronous Output Enable
•
Boundary Scan (JTAG) IEEE 1149.1 Compatible
•
Differential Clock Inputs
•
Optional x 18 or x 36 organization
•
MCM69R736A/818A–5 = 5 ns
MCM69R736A/818A–6 = 6 ns
MCM69R736A/818A–7 = 7 ns
MCM69R736A/818A–8 = 8 ns
•
Sleep Mode Operation (ZZ Pin)
•
119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM69R736A/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM69R736A
MCM69R818A
ZP PACKAGE
PBGA
CASE 999–01
REV 1
8/20/97
©
Motorola, Inc. 1997
MCM69R736A
•
MCM69R818A
2
MOTOROLA FAST SRAM
ADDRESS
REGISTERS
SA
CK
SW
SBx
CONTROL
LOGIC
DATA IN
REGISTER
MEMORY
ARRAY
G
SW
REGISTERS
DATA OUT
REGISTER
DQ
SS
SS
REGISTERS
FUNCTIONAL BLOCK DIAGRAM
PIN ASSIGNMENTS
MCM69R736A
6
5
4
3
2
1
7
B
C
VSS
G
A
D
E
F
H
J
VSS
VSS
SBb
VSS
SA
VSS
VSS
VSS
SA
SA
SA
SA
SA
SA
SA
SA
NC
SA
SA
NC
NC
NC
DQb
SA
SA
NC
ZZ
SW
DQa
DQa
VDDQ
VDDQ
DQb
VDDQ
DQb
DQb
DQa
DQa
VDD
VDD
TDO
SA
TDI
TMS
NC
TCK
DQd
DQd
VSS
SA
CK
VSS
DQa
DQa
SA
VSS
DQd
DQd
VDDQ DQd VSS
NC
DQa
DQa
SBa
SBd
DQd
DQd
DQd
DQd
VSS
CK
VSS
DQc
DQa
VDD
Vref
VDD
Vref
VDD
VDDQ
DQc
VSS
NC
DQb
DQb
DQb
NC
SBc
DQc
DQc
VDDQ DQc VSS
G
DQb
SS
VSS
DQc
DQc
DQc
VSS
ZQ
DQb
VDD
NC
NC
NC
SA
NC
NC
K
L
M
N
P
R
T
U
VDDQ
VDDQ
NC
VDDQ
VDDQ
NC
6
5
4
3
2
1
7
B
C
VSS
G
A
D
E
F
H
J
VSS
VSS
VSS
VSS
SA
VSS
VSS
VSS
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
NC
NC
NC
SA
SA
NC
ZZ
SW
NC
NC
VDDQ
VDDQ
NC
VDDQ
DQa
DQa
DQa
DQa
VDD
VDD
TDO
NC
TDI
TMS
NC
TCK
NC
DQb
VSS
SA
CK
VSS
NC
DQa
SA
VSS
NC
DQb
VDDQ DQb VSS
NC
NC
DQa
SBa
VSS
NC
DQb
NC
DQb
VSS
CK
VSS
DQb
NC
VDD
Vref
VDD
Vref
VDD
VDDQ
NC
VSS
NC
DQa
DQa
NC
NC
SBb
DQb
NC
VDDQ
NC
VSS
G
NC
SS
VSS
DQb
NC
DQb
NC
VSS
ZQ
DQa
VDD
NC
NC
NC
SA
NC
NC
K
L
M
N
P
R
T
U
VDDQ
VDDQ
NC
VDDQ
VDDQ
NC
MCM69R818A
DQc
TOP VIEW
MCM69R736A
•
MCM69R818A
3
MOTOROLA FAST SRAM
MCM69R736A PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
Type
Description
4K
CK
Input
Address, data in and control input register clock. Active high.
4L
CK
Input
Address, data in and control input register clock. Active low.
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
DQx
I/O
Synchronous Data I/O.
4F
G
Input
Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge.
5L, 5G, 3G, 3L
(a), (b), (c), (d)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4M
SW
Input
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
4U
TCK
Input
Test Clock (JTAG).
3U
TDI
Input
Test Data In (JTAG).
5U
TDO
Output
Test Data Out (JTAG).
2U
TMS
Input
Test Mode Select (JTAG).
4D
ZQ
Input
Programmable Output Impedance: Programming pin.
7T
ZZ
Input
Enables sleep mode, active high.
4C, 2J, 4J, 6J, 4R, 5R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
Output Power Supply: provides operating power for output buffers.
3J, 5J
Vref
Supply
Input Reference: provides reference voltage for input buffers.
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R
VSS
Supply
Ground.
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U
NC
—
No Connection: There is no connection to the chip.
MCM69R736A
•
MCM69R818A
4
MOTOROLA FAST SRAM
MCM69R818A PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
Type
Description
4K
CK
Input
Address, data in and control input register clock. Active high.
4L
CK
Input
Address, data in and control input register clock. Active low.
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
I/O
Synchronous Data I/O.
4F
G
Input
Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge.
5L, 3G
(a), (b)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4M
SW
Input
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
4U
TCK
Input
Test Clock (JTAG).
3U
TDI
Input
Test Data In (JTAG).
5U
TDO
Output
Test Data Out (JTAG).
2U
TMS
Input
Test Mode Select (JTAG).
4D
ZQ
Input
Programmable Output Impedance: Programming pin.
7T
ZZ
Input
Enables sleep mode, active high.
4C, 2J, 4J, 6J, 4R, 5R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
Output Power Supply: provides operating power for output buffers.
3J, 5J
Vref
Supply
Input Reference: provides reference voltage for input buffers.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R
VSS
Supply
Ground.
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
2D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,
2H, 4H, 7H, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U
NC
—
No Connection: There is no connection to the chip.
MCM69R736A
•
MCM69R818A
5
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS, See Note 1)
Rating
Symbol
Value
Unit
Core Supply Voltage
VDD
– 0.5 to + 4.6
V
Output Supply Voltage
VDDQ
– 0.5 to VDD + 0.5
V
Voltage On Any Pin
Vin
– 0.5 to VDD + 0.5
V
Input Current (per I/O)
Iin
±
50
mA
Output Current (per I/O)
Iout
±
70
mA
Power Dissipation (See Note 2)
PD
—
W
Operating Temperature
TA
0 to + 70
°
C
Temperature Under Bias
Tbias
–10 to + 85
°
C
Storage Temperature
Tstg
– 55 to + 125
°
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability will be dependent upon package characteristics and use
environment. See enclosed thermal impedance data.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (Still Air)
R
θ
JA
53
°
C/W
1, 2
Junction to Ambient (@200 ft/min)
Single Layer Board
R
θ
JA
38
°
C/W
1, 2
Junction to Ambient (@200 ft/min)
Four Layer Board
R
θ
JA
22
°
C/W
Junction to Board (Bottom)
R
θ
JB
14
°
C/W
3
Junction to Case (Top)
R
θ
JC
5
°
C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
CLOCK TRUTH TABLE
K
ZZ
SS
SW
SBa
SBb
SBc
SBd
DQ (n)
DQ (n+1)
Mode
L – H
L
L
H
X
X
X
X
X
Dout 0–35
Read Cycle All Bytes
L – H
L
L
L
L
H
H
H
High–Z
Din 0–8
Write Cycle 1st Byte
L – H
L
L
L
H
L
H
H
High–Z
Din 9–17
Write Cycle 2nd Byte
L – H
L
L
L
H
H
L
H
High–Z
Din 18–26
Write Cycle 3rd Byte
L – H
L
L
L
H
H
H
L
High–Z
Din 27–35
Write Cycle 4th Byte
L – H
L
L
L
L
L
L
L
High–Z
Din 0–35
Write Cycle All Bytes
L – H
L
L
L
H
H
H
H
High–Z
High–Z
Abort Write Cycle
L – H
L
H
H
X
X
X
X
X
High–Z
Deselect Cycle
L – H
L
H
L
X
X
X
X
High–Z
High–Z
Deselect Cycle
X
H
X
X
X
X
X
X
High–Z
High–Z
Sleep Mode
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
MCM69R736A
•
MCM69R818A
6
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(See Notes 1 through 4)
Parameter
Symbol
Min
Typical
–5
Typical
–6
Typical
–7
Typical
–8
Max
Unit
Notes
Input Reference DC Voltage
Vref (dc)
0.6
—
—
—
—
1.1
V
11
Core Power Supply Voltage
VDD
3.15
—
—
—
—
3.6
V
Output Driver Supply Voltage
VDDQ
1.4
—
—
—
—
1.6
V
Active Power Supply Current
(x18)
(x36)
IDD1
—
—
350
460
330
430
300
390
290
370
450
560
mA
5
Quiescent Active Power Supply Current
IDD2
—
190
190
190
190
250
mA
6, 10
Active Standby Power Supply Current
ISB1
—
160
160
160
160
250
mA
7
Quiescent Standby Power Supply Current
ISB2
—
140
140
140
140
230
mA
8, 10
Sleep Mode Power Supply Current
ISB3
—
TBD
TBD
TBD
TBD
TBD
mA
9, 10
NOTES:
1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.
2. Supply voltage applied to VDD connections.
3. Supply voltage applied to VDDQ connections.
4. All power supply currents measured with outputs open or deselected.
5. VDD = VDD (max), tKHKH = tKHKH (min), SS registered active, 50% read cycles.
6. VDD = VDD (max), tKHKH = dc, SS registered active.
7. VDD = VDD (max), tKHKH = tKHKH (min), SS registered inactive.
8. VDD = VDD (max), tKHKH = dc, SS registered inactive, ZZ low.
9. VDD = VDD (Max), tKHKH = dc, SS registered inactive, ZZ high.
10. 200 mV
≥
Vin
≥
VDDQ – 200 mV.
11. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Notes
DC Input Logic High
VIH (dc)
Vref + 0.1
VDD + 0.3
V
DC Input Logic Low
VIL (dc)
– 0.3
Vref – 0.1
V
1
Input Leakage Current
Ilkg(1)
—
±
5
µ
A
2
Clock Input Signal Voltage
Vin (dc)
– 0.3
VDD + 0.3
V
Clock Input Differential Voltage
VDIF (dc)
0.2
VDD + 0.6
V
3
Clock Input Common Mode Voltage Range (See Figure 2)
VCM (dc)
0.68
1.1
V
4
Clock Input Crossing Point Voltage Range (See Figure 2)
VX
0.68
1.1
V
NOTES:
1. Inputs may undershoot to –0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns). See Figure 2.
2. 0 V
≤
Vin
≤
VDDQ for all pins.
3. Minimum instantaneous differential input voltage required for differential input clock operation.
4. Maximum rejectable common mode input voltage variation.
MCM69R736A
•
MCM69R818A
7
MOTOROLA FAST SRAM
PROGRAMMABLE IMPEDANCE OUTPUT BUFFER OPERATION
Refer to Functional Operation section for more detailed explanation.
DC OUTPUT BUFFER CHARACTERISTICS – PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(0
°
C
≤
TA
≤
70
°
C, ZQ = IZQ (out) (RQ)) (See Notes 5 and 6)
Parameter
Symbol
Min
Max
Unit
Notes
Output Logic Low
VOL
VDDQ/2 – 0.025
VDDQ/2 + 0.025
V
1
Output Logic High
VOH
VDDQ/2 – 0.025
VDDQ/2 + 0.025
V
2
Light Load Output Logic Low
VOL1
VSS
0.2
V
3
Light Load Output Logic High
VOH1
VDDQ – 0.2
VDDQ
V
4
NOTES:
1. IOL = (VDDQ/2)/(RQ/5) for values of RQ = 175
Ω
≤
RQ
≤
350
Ω.
2. | IOH | = (VDDQ/2)/(RQ/5) for values of RQ = 175
Ω ≤
RQ
≤
350
Ω.
3. IOL
≤
100
µ
A.
4. | IOH |
≤
100
µ
A.
5. The impedance controlled mode is expected to be used in point–to–point applications, driving high impedance inputs.
6. The ZQ pin is connected through RQ to VSS for the controlled impedance mode.
DC OUTPUT BUFFER CHARACTERISTICS – MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(
0
°
C
≤
TA
≤
70
°
C, ZQ = VDD)
(See Notes 5 and 6)
Parameter
Symbol
Min
Max
Unit
Notes
Output Logic Low
VOL2
VSS
0.4
V
1
Output Logic High
VOH2
VDDQ – 0.4
VDDQ
V
2
Light Load Output Logic Low
VOL3
VSS
0.2
V
3
Light Load Output Logic High
VOH3
VDDQ – 0.2
VDDQ
V
4
NOTES:
1. IOL
≤
8 mA
2. | IOH |
≤
8 mA
3. IOL
≤
100
µ
A
4. | IOH |
≤
100
µ
A
5. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC
Standard JESD8–6 Class 1.
6. The ZQ pin is connected to VDD to enable the minimum impedance mode.
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V,
0
°
C
≤
TA
≤
70
°
C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Symbol
Typ
Max
Unit
Input Capacitance
Cin
4
5
pF
Input/Output Capacitance
CI/O
7
8
pF
CK, CK Capacitance
CCK
4
5
pF
MCM69R736A
•
MCM69R818A
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
Input Pulse Levels
0.25 to 1.25 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
1 V/ns (20% to 80%)
. . . . . . . . . . . . . . . . . . . . . .
Input Timing Measurement Reference Level