SP574B_674B_1674B

SP574B/674B/1674B/774B

12–Bit Sampling A/D Converters

Complete Monolithic 12–Bit A/D Converters

with Sample–Hold, Reference, Clock and Tri–

state Outputs

Full Nyquist Sampling at All Sample Rates

Choice of Sampling Rates — 40kHz, 66kHz,

100kHz or 125kHz

Low Power Dissipation — 110mW

12–Bit Linearity Over Temperature

Commercial, Industrial and Military Tempera-

ture Ranges

Next–Generation Replacement for 574A, 674A,

1674A, 774A Devices

STS

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DGND

VLOGIC 12/8

R/C

VCC

REF

OUT

AGND

REF

VEE

BIP

OFF

10V

20V

NIBBLE A

NIBBLE B

NIBBLE C

THREE–STATE BUFFERS AND CONTROL

N/C

7.5K

15K

7.5K

OFFSET/GAIN

TRIM

12–BIT

CAPACITANCE

DAC

COMP

REF

CONTROL LOGIC

12–BIT SAR

OSC

DESCRIPTION…

The SP574B/674B/1674B/774B (SPx74B) Series are complete 12–bit successive–approxi-

mation A/D converters integrated on a single die with tri-state output latches, an internal

reference, clock and a sample–hold. The new “B–Series” features true Nyquist sampling while

maintaining compatibility with prior versions. They are drop–in replacements for the older 574A/

674A/1674A/774A type devices.

SP574B/674B/1674B/774B

12–Bit Sampling A/D Converters

SP574B/674B/1674B/774B

12–Bit Sampling A/D Converters

ABSOLUTE MAXIMUM RATINGS

to Digital Common .................................................. 0 to +16.5V

LOGIC

to Digital Common ................................................... 0 to +7V

Analog Common to Digital Common .........................................

Control Inputs to Digital Common ................. –0.5V to V

LOGIC

+0.5V

(CE, CS, A

, 12/8, R/C)

Analog Input Voltage Range ...........................................

30%

Analog Inputs to Analog Common ......................................

16.5V

(REF IN, BIP OFF, 10V

)

20V

to Analog Common ........................................................

24V

REF OUT ............................................... Indefinite short to common

................................................................... Momentary short to V

Power Dissipation ............................................................. 1000mW

Lead Temperature, Soldering .................................. 300˚C, 10Sec

J/C ..................................................................................... 45˚C/W

MTBF–25˚C Ground Base ................................ 2.915 million hours

MTBF–125˚C Missile Launch ...................... 10.16 thousand hours

•

Inputs exceeding +30% or –30% of FS will cause erratic performance.

CAUTION:

ESD (ElectroStatic Discharge) sensitive

device. Permanent damage may occur on

unconnected devices subject to high energy

electrostatic fields. Unused devices must be

stored in conductive foam or shunts.

Personnel should be properly grounded prior

to handling this device. The protective foam

should be discharged to the destination

socket before devices are removed.

SPECIFICATIONS

(Typical @ 25

C with V

= +15V, V

= 0V, V

LOGIC

= +5V unless otherwise noted.)

PARAMETER

MIN.

TYP.

MAX.

UNIT

CONDITIONS

RESOLUTION

All models

Bits

ANALOG INPUTS

Input Ranges

Bipolar

Unipolar

0 to +10, 0 to +20

Input Impedance

SP574B/SP674B

10 Volt Input

3.75

6.25

Ω

20 Volt Input

Ω

SP1674B/SP774B

10 Volt Input

1.875

3.125

Ω

20 Volt Input

7.45

12.42

Ω

Nyquist Frequency

SP574B

kHz

SP674B

kHz

SP1674B

kHz

SP774B

62.5

kHz

DIGITAL INPUTS

Logic Inputs CE, CS R/C, A

, 12/8

Logic 1

+2.4

+5.5

Logic 0

–0.3

+0.8

Current

0.1

–0.3V to +5.5V Input

0V to +5.5V Input

Capacitance

12/8 Control Input

Hardwire to V

LOGIC

or DIGITAL COMMON

DIGITAL OUTPUTS

Logic Outputs DB

–DB

, STS

Logic 1

+2.4

SOURCE

≤

500

Logic 0

+0.4

SINK

≤

1.6mA

Leakage (High Z State)

Data bits only

Capacitance

Parallel Data Output Codes

Unipolar

Positive true binary

Bipolar

Positive true offset binary

INTERNAL REFERENCE

Output Voltage

10.00

0.1

Output Current

Note 1

SP574B/674B/1674B/774B

12–Bit Sampling A/D Converters

SPECIFICATIONS

(continued)

(Typical @ 25

C with V

= +15V, V

= 0V, V

LOGIC

= +5V unless otherwise noted.)

PARAMETER

MIN.

TYP.

MAX.

UNIT

CONDITIONS

CONVERSION TIME

SP574B

12–Bit Conversion

8–Bit Conversion

SP674B

12–Bit Conversion

8–Bit Conversion

11.2

SP1674B

12–Bit Conversion

8–Bit Conversion

7.6

SP774B

12–Bit Conversion

8–Bit Conversion

ACCURACY

Linearity Error

–A, –J, –S

1.0

LSB

@ 25

C and T

MIN

to T

MAX

–B, –K, –T

0.5

LSB

@ 25

C and T

MIN

to T

MAX

Differential Linearity Error

Note 2

–A, –J, –S

Bits

@ 25

Bits

MIN

to T

MAX

–B, –K, –T

Bits

@ 25

Bits

MIN

to T

MAX

Offset

Note 3

Unipolar

LSB

Bipolar

–A, –J, –S

LSB

–B, –K, –T

LSB

Full Scale (Gain) Error

% of full scale; T

MIN

to T

MAX

0.3

%FS

Note 4

–A

0.6

%FS

No adjustment @ 25

0.3

%FS

With adjustment @ 25

–B

0.45

%FS

No adjustment @ 25

0.15

%FS

With adjustment @ 25

–J

0.5

%FS

No adjustment @ 25

0.22

%FS

With adjustment @ 25

–K

0.4

%FS

No adjustment @ 25

0.12

%FS

With adjustment @ 25

–S

0.8

%FS

No adjustment @ 25

0.5

%FS

With adjustment @ 25

–T

0.6

%FS

No adjustment @ 25

0.25

%FS

With adjustment @ 25

STABILITY

Unipolar Offset

–J

ppm/

MIN

to T

MAX

–K, –A, –S

ppm/

MIN

to T

MAX

–B, –T

2.5

ppm/

MIN

to T

MAX

Bipolar Offset

–J, –A, –S

ppm/

MIN

to T

MAX

–K, –B, –T

ppm/

MIN

to T

MAX

Gain (Scale Factor)

–J, –A, –S

ppm/

MIN

to T

MAX

–K, –B, –T

ppm/

MIN

to T

MAX

SP574B/674B/1674B/774B

12–Bit Sampling A/D Converters

TYPICAL AC DYNAMICS

Measurement/Model

SP574B

SP674B

SP1674B

SP774B

Unit

Test Conditions:

Sampling Rate

100

125

kHz

Input Frequency (F

)

kHz

SFDR

THD

-80

-77

-76

SINAD

SNR

72.5

Note:

Refer to Figure 10, for typical FFT at Nyquist sampling rate.

SPECIFICATIONS

(continued)

(Typical @ 25

C with V

= +15V, V

= 0V, V

LOGIC

= +5V unless otherwise noted.)

PARAMETER

MIN.

TYP.

MAX.

UNIT

CONDITIONS

POWER REQUIREMENTS

LOGIC

+4.5

+5.5

LOGIC

SP574B

SP674B

SP1674B

SP774B

+11.4

+16.5

SP574B

SP674B

SP1674B

12.5

SP774B

12.5

POWER DISSIPATION

SP574B

110

150

SP674B

110

150

SP1674B

155

200

SP774B

155

200

ENVIRONMENTAL

Operating Temperature Range

–J, –K

+70

–A, –B

–40

+85

–S, –T

–55

+125

Storage Temperature Range

–J, –K

–40

+85

–A, –B, –S, –T

–65

+150

Notes:

Available for external loads. External load should not change during conversion. When supplying an

external load and operating on a +12V supply, a buffer amplifier must be provided for the reference

output.

Minimum resolution for which no missing codes are guaranteed.

Externally adjustable to zero. See

Calibration information.

Fixed 50

Ω

resistor between REF OUT and REF IN.

Specifications are identical for all models unless otherwise noted.

SP574B/674B/1674B/774B

12–Bit Sampling A/D Converters

CIRCUIT OPERATION…

The SPx74B are complete monolithic capacitor

DAC–based 12–bit analog-to-digital convert-

ers with integral voltage reference, comparator,

successive–approximation register (SAR),

sample–and–hold, clock, output buffers and

control circuitry. The high level of integration

of the SPx74B Series means they require few

external components.

When the control section of the SPx74B initiates

a conversion command, the clock is enabled and

the successive–approximation register is reset to

all zeros. Once the conversion cycle begins, it can

not be stopped or restarted and data is not available

from the output buffers. The SAR, timed by the

clock, sequences through the conversion cycle and

returns an end–of–convert flag to the control sec-

tion of the ADC. The clock is then disabled by the

control section, the output status goes low, and the

control section is enabled to allow the data to be

read by external command.

The internal SPx74B 12–bit CDAC is sequenced

by the SAR starting from the MSB to the LSB at

the beginning of the conversion cycle to provide

an output voltage from the CDAC that is equal

to the input signal voltage (which is divided by

the input voltage divider network). The com-

parator determines whether the addition of each

successively–weighted bit voltage causes the

CDAC output voltage summation to be greater

or less than the input voltage; if the sum is less,

the bit is left on; if more, the bit is turned off.

After testing all the bits, the SAR contains a 12–

bit binary code which accurately represents the

input signal to within

⁄

LSB.

The internal reference provides the voltage refer-

ence to the CDAC with excellent stability over

temperature and time. The reference is trimmed

to 10.00 Volts

1% and can supply up to 2mA to

an external load in addition to that required to

drive the reference input resistor (1mA) and

offset resistor (1mA) when operating with

15V

supplies. If the SPx74B is used with

12V

supplies, or if external current must be supplied

over the full temperature range, an external

buffer amplifier is recommended. Any external

load on the SPx74B reference must remain

constant during conversion.

FEATURES…

The SPx74B Series feature standard bipolar

and unipolar input ranges of 10V and 20V. Input

ranges are controlled by a bipolar offset pin and

laser-trimmed for specified linearity, gain and

offset accuracy. Power requirements are +5V

and +12V to +15V with a maximum dissipation

of 150mW at the specified voltages. Conversion

times of 8

s, 10

s, 15

s and 25

s are available,

as are units with 10, 25 or 50ppm/

C tempera-

ture coefficients for flexible matching to spe-

cific application requirements.

The SPx74B Series are available in nine prod-

uct grades for each conversion time. The –J

and –K models are specified over 0˚C to +

70˚C commercial temperature range; the –A

and –B models are specified over the –40˚C

to +85˚C industrial temperature range; the –S

and –T models are specified over the –55˚C to

+125˚C military temperature range. Package

options include 28–pin CDIP, 28–pin plastic

DIP (both narrow and wide), 28-pin PLCC

and 28–pin SOIC.

PIN ASSIGNMENTS…

PIN

FUNCTION

PIN

FUNCTION

LOGIC

STS

12/8

(MSB)

R/C

REF OUT

ANA GND(AC)

REF IN

N/C*

BIP OFF

10V

(LSB)

20V

DIG. GND

*This pin is not connected inside the device so it can

be tied to –15V, ground, or left floating.

SP574B/674B/1674B/774B

12–Bit Sampling A/D Converters

SAMPLE–AND–HOLD FUNCTION

Although there is no sample–and–hold circuit in

the classical sense, the sampling nature of the

capacitive DAC makes the SPx74B appear to have

a built–in sample–and–hold. The sample–and–

hold function of the CDAC architecture is opti-

mized to provide full Nyquist sampling at any

maximum sampling rate. Because the S/H func-

tion is included in the ADC circuitry, the majority

of the S/H specifications are included within the A/

D specifications.

Note that some system architectures may use an

external sample–and–hold. The built–in S/H func-

tion of the SPx74B will provide additional isola-

tion. Once the internal sample is taken by the

CDAC capacitance, the input of the SPx74B is

disconnected from the input. This prevents tran-

sients occurring during conversion from being

inflicted upon the attached buffer. All other 574/

674–type circuits will cause a transient load cur-

rent on the input which will upset the buffer output

and may add error to the conversion itself. In

addition, the isolation of the input after the acqui-

sition time in the SPx74B allows you the opportu-

nity to release the HOLD on an external sample–

and–hold and start it tracking the next sample. This

will increase system throughput with your existing

components.

When using an external S/H, the SPx74B acts as

any other 574–type device because the internal S/

H is transparent. The sample/hold function in the

SPx74B is inherent to the capacitor DAC struc-

ture, and its timing characteristics are determined

by the internally generated clock. However, for

multiplexer operation, the internal S/H may elimi-

nate the need for an external S/H. The operation of

the S/H function is internal to the SPx74B and is

USING THE SPX74B SERIES

Typical Interface Circuit

The SPx74B is a complete A/D converter that is

fully operational when powered up and issued a

Start Convert Signal. Only a few external compo-

nents are necessary. The SPx74B Series have four

standard input ranges: 0V to +10V, 0V to +20V,

5V and

10V. Figure 2 depicts a typical interface

circuit for operating the SPx74B in a unipolar

input mode. Figure 3 depicts a typical interface

circuit for operating the SPx74B in a bipolar input

mode. Further information is given in the follow-

ing sections on these connections, but first a few

considerations concerning board layout to achieve

the best operation.

For each application of this device, strict attention

must be given to power supply decoupling, board

layout (to reduce pickup between analog and digi-

tal sections), and grounding. Digital timing, cali-

bration and the analog signal source must be

considered for correct operation.

To achieve specified accuracy, a double–sided

printed circuit board with a copper ground plane

on the component side is recommended. Keep

analog signal traces away from digital lines. It is

best to lay the PC board out such that there is an

analog section and a digital section with a single

point ground connection between the two through

an RF bead. If this is not possible, run analog

controlled through the normal R/C control line

(refer to Figure 1). When the R/C line makes a

negative transition, the SPx74B starts the timing

of the sampling and conversion. The first two

clock cycles are allocated to signal acquisition of

the input by the CDAC (this time is defined as

ACQ

). Following these two cycles, the input sample

is taken and held. The A/D conversion follows this

cycle with the duration controlled by the internal

clock cycle, which is determined by the specific

product model. Note that because the sample is

taken relative to the R/C transition, t

ACQ

is also the

traditional “aperture delay” of this internal sample

and hold. Since t

ACQ

is measured in clock cycles,

its duration will vary with the internal clock fre-

quency.

Offset, gain and linearity errors of the S/H circuit,

as well as the effects of its droop rate, are included

in the overall specs for the SPx74B.

R/C

WAIT FOR

CONVERT SIGNAL

WAIT FOR

BUS READ

CONVERSION

VIN

CDAC VOLTAGE

0 VOLTS

t(ACQ)

ACQUISITION

TIME

ACQUISITION TIME =

APERTURE DELAY TIME =

0.12 x tCONVERT

Figure 1. Sample–and–Hold Function

SP574B/674B/1674B/774B

12–Bit Sampling A/D Converters

STS

DGND

12/8

R/C

THREE–STATE BUFFERS AND CONTROL

NIBBLE A

NIBBLE B

NIBBLE C

21 20

19 18

17 16

OUTPUT BITS

MSB

LSB

CONTROL

LOGIC

OSCILLATOR

12–BITS

SAMPLE/HOLD

CDAC

LSB

MSB

OFFSET/GAIN

TRIM NETWORK

REF

AMP

VLOGIC

+5V

VCC

VEE

AGND

+15V

N.C.

VREF

OUT

VREF

100

Ω

100K

Ω

100K

Ω

-15V

+15V

100

Ω

10V

20V

BIP

OFF

ANALOG

INPUTS

0 TO 10V

0 TO 20V

12–BIT SAR

COMP

STROBE

10µF

0.1µF

10µF

0.1µF

Figure 2. Unipolar Input Connections

signals between ground traces and cross digital

lines at right angles only.

Grounding Considerations

Any ground path from the analog and digital

ground should be as low resistance as possible to

accommodate the ground currents present with

this device.

The analog ground current is approximately

6mA DC while the digital ground is 3mA DC.

The analog and digital common pins should be

tied together as close to the package as possible