DATA SHEET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT390
Dual decade ripple counter
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990
2
Philips Semiconductors
Product specification
Dual decade ripple counter
74HC/HCT390
FEATURES
•
Two BCD decade or bi-quinary counters
•
One package can be configured to divide-by-2, 4, 5, 10,
20, 25, 50 or 100
•
Two master reset inputs to clear each decade counter
individually
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT390 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters
divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5
sections. These sections are normally used in a BCD
decade or bi-quinary configuration, since they share a
common master reset input (nMR). If the two master reset
inputs (1MR and 2MR) are used to simultaneously clear all
8 bits of the counter, a number of counting configurations
are possible within one package. The separate clocks
(nCP
0
and nCP
1
) of each section allow ripple counter or
frequency division applications of divide-by-2, 4, 5, 10, 20,
25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of
the clock inputs (nCP
0
and nCP
1
). For BCD decade
operation, the nQ
0
output is connected to the nCP
1
input
of, the divide-by-5 section. For bi-quinary decade
operation, the nQ
3
output is connected to the nCP
0
input
and nQ
0
becomes the decade output.
The master reset inputs (1MR and 2MR) are active HIGH
asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the “1”
and “2” prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four
outputs LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µ
W):
P
D
= C
PD
×
V
CC
2
×
f
i
+ ∑
(C
L
×
V
CC
2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC
2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
C
L
= 15 pF; V
CC
= 5 V
nCP
0
to nQ
0
14
18
ns
nCP
1
to nQ
1
15
19
ns
nCP
1
to nQ
2
23
26
ns
nCP
1
to nQ
3
15
19
ns
nMR to Q
n
16
18
ns
f
max
maximum clock frequency nCP
0
, nCP
1
66
61
MHz
C
I
input capacitance
3.5
3.5
pF
C
PD
power dissipation capacitance per counter
notes 1 and 2
20
21
pF
December 1990
6
Philips Semiconductors
Product specification
Dual decade ripple counter
74HC/HCT390
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
I
CC
category: MSI
Note to HCT types
The value of additional quiescent supply current (
∆
I
CC
) for a unit load of 1 is given in the family specifications.
To determine
∆
I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
INPUT
UNIT LOAD COEFFICIENT
nCP
0
nCP
1
, nMR
0.45
0.60
SYMBOL
PARAMETER
T
amb
(
°
C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+
25
−
40 to
+
85
−
40 to
+
125
min.
typ.
max. min. max. min.
max.
t
PHL
/ t
PLH
propagation delay
nCP
0
to nQ
0
21
34
43
51
ns
4.5
Fig.6
t
PHL
/ t
PLH
propagation delay
nCP
1
to nQ
1
22
38
48
57
ns
4.5
Fig.6
t
PHL
/ t
PLH
propagation delay
nCP
1
to nQ
2
30
51
64
77
ns
4.5
Fig.6
t
PHL
/ t
PLH
propagation delay
nCP
1
to nQ
3
22
38
48
57
ns
4.5
Fig.6
t
PHL
propagation delay
nMR to nQ
n
21
36
45
54
ns
4.5
Fig.7
t
THL
/ t
TLH
output transition time
7
15
19
22
ns
4.5
Fig.6
t
W
clock pulse width
nCP
0
, nCP
1
18
8
23
27
ns
4.5
Fig.6
t
W
master reset pulse width
HIGH
17
10
21
26
ns
4.5
Fig.7
t
rem
removal time
nMR to nCP
n
15
8
19
22
ns
4.5
Fig.7
f
max
maximum clock pulse
frequency
nCP
0
, nCP
1
27
55
22
18
MHz
4.5
Fig.6
December 1990
7
Philips Semiconductors
Product specification
Dual decade ripple counter
74HC/HCT390
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6
Waveforms showing the clock (nCP
n
) to output (nQ
n
) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7
Waveforms showing the master reset (nMR) pulse width, the master reset to output (nQ
n
) propagation
delays and the master reset to clock (nCP
n
) removal time.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
