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1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

C-bus controlled TV input processor

TDA9321H

FEATURES

•

Multistandard Vision IF (VIF) circuit with Phase-Locked

Loop (PLL) demodulator

•

Sound IF (SIF) amplifier with separate input for single

reference Quasi Split Sound (QSS) mode and separate

Automatic Gain Control (AGC) circuit

•

AM demodulator without extra reference circuit

•

Switchable group delay correction circuit which can be

used to compensate the group delay pre-correction of

the B/G TV standard in multistandard TV receivers

•

Several (I

C-bus controlled) switch outputs which can

be used to switch external circuits such as sound traps,

etc.

•

Flexible source selection circuit with 2 external

CVBS inputs, 2 Luminance (Y) and Chrominance (C)

(or additional CVBS) inputs and 2 independently

switchable outputs

•

Comb filter interface with CVBS output and Y/C input

•

Integrated chrominance trap circuit

•

Integrated luminance delay line with adjustable delay

time

•

Integrated chrominance band-pass filter with switchable

centre frequency

•

Multistandard colour decoder with 4 separate pins for

crystal connection and automatic search system

•

PALplus helper demodulator

•

Possible blanking of the helper signals for PALplus and

EDTV-2

•

Internal baseband delay line

•

Two linear RGB inputs with fast blanking; the

RGB signals are converted to YUV signals before they

are supplied to the outputs; one of the RGB inputs can

also be used as YUV input

•

Horizontal synchronization circuit with switchable time

constant for the PLL and Macrovision/subtitle gating

•

Horizontal synchronization pulse output or clamping

pulse input/output

•

Vertical count-down circuit

•

Vertical synchronization pulse output

•

Two-level sandcastle pulse output

•

C-bus control of various functions

•

Low dissipation.

GENERAL DESCRIPTION

The TDA9321H (see Fig.1) is an input processor for

‘High-end’ television receivers. It contains the following

functions:

•

Multistandard IF amplifier with PLL demodulator

•

QSS-IF amplifier and AM sound demodulator

•

CVBS and Y/C switch with various inputs and outputs

•

Multistandard colour decoder which can also decode the

PALplus helper signal

•

Integrated baseband delay line (64

•

Sync processor which generates the horizontal and

vertical drive pulses for the feature box

(100 Hz applications) or display processor

(50 Hz applications).

The supply voltage for the TDA9321H is 8 V.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

TDA9321H

QFP64

plastic quad ﬂat package; 64 leads (lead length 1.95 mm);

body 14

2.8 mm

SOT319-2

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

C-bus controlled TV input processor

TDA9321H

QUICK REFERENCE DATA

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Supply

supply voltage (pins V

and V

)

7.2

8.0

8.8

supply current (pins V

and V

)

−

120

−

Input signals

i(VIF)(rms)

VIF ampliﬁer sensitivity (RMS value)

−

i(SIF)(rms)

SIF ampliﬁer sensitivity (RMS value)

−

i(CVBS/Y)(p-p)

CVBS or Y input signal (peak-to-peak value)

−

1.0

−

i(C)(p-p)

chrominance input signal (burst amplitude)

(peak-to-peak value)

−

0.3

−

i(RGB)(p-p)

RGB input signal (peak-to-peak value)

−

0.7

−

Output signals

o(VIFO)(p-p)

demodulated CVBS output signal (peak-to-peak value)

−

2.5

−

o(CVBSPIP)(p-p)

CVBS output signal for Picture-In-Picture

(peak-to-peak value)

−

1.0

−

o(CVBSTXT)(p-p)

CVBS output signal for teletext (peak-to-peak value)

−

2.0

−

o(TAGC)

tuner AGC output current

−

o(QSS)(rms)

QSS output signal (RMS value)

−

100

−

o(AM)(rms)

demodulated AM sound output signal (RMS value)

−

500

−

o(V)(p-p)

−

V output signal (peak-to-peak value)

−

1.05

−

o(U)(p-p)

−

U output signal (peak-to-peak value)

−

1.33

−

o(Y)(b-w)

Y output signal (black-to-white value)

−

1.0

−

o(hor)

horizontal pulse output

−

o(ver)

vertical pulse output

−

o(sc)(p-p)

subcarrier output signal (peak-to-peak value)

−

250

−

1998

Dec

Philips Semiconductors

Preliminary speciﬁcation

C-bus controlled TV input processor

TDA9321H

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BLOCK DIAGRAM

MGR473

ndbook, full pagewidth

VIFVCO2

VIFVCO1

TAGC

AFC

TOP

mute

Y/CVBS

helper

hue

fsc

switch control

VIF AMPLIFIER

AND PLL

DEMODULATOR

AGC/AFC

VIDEO AMPLIFIER

MUTE

SUPPLY

PULSE

GENERATOR

SOUND

TRAP

GROUP DELAY

CORRECTION

VIDEO SWITCHES

AND

CONTROL

VIFO

GDI

GDO

CVBS/Y4

SW1

CVBS/Y3

SW0

CVBS2

AV2

CVBS1

AV1

CVBSint

VIF1

VIF2 DECVIF

VCO AND

HORIZONTAL

PLL

VIDEO

IDENTIFICATION

IDENT

SYNC

SEPARATOR

AUTOMATIC

CHROMINANCE

CONTROL

CLOCHE

FILTER

VERTICAL

DIVIDER

SYNC

IN-LOCK

DETECTOR

FILTER

TUNING

C-BUS

TRANSCEIVER

Y-DELAY

Y-delay

RGB2

Y-SWITCH

AND TRAPS

SECAM

DECODER

RGB MATRIX

Y/U/V

SWITCH

BASEBAND

DELAY LINE

PAL(NTSC)/

SECAM SWITCH

Y/C

DETECTOR

BANDPASS

FILTER

subcarrier

COMB FILTER

PAL/NTSC

PLL

HUE CONTROL

SYSTEM

IDENTIFICATION

PAL/NTSC

DEMODULATOR

SIF AMPLIFIER

AGC

QSS MIXER

AM DEMODULATOR

SIF1

HA/CLP

SCO

SCL

SDA

GI1

RI1

BI1

RGB1

SIF2

DECSIF

VP1

QSS/AM

VP2 DECDIG

DECBG

VIFPLL

VERTICAL

SYNC

SEPARATOR

BI2

GI2

RI2

B-Y

R-Y

DECSEC

PH1LF

REFO

CCF

YCF

SYS2

SYS1

CVBSCF

CVBSPIP

CVBSTXT

LFBP

XTALD

XTALC

XTALB

XTALA

GND3

GND2

GND1

TDA9321H

Fig.1 Block diagram.

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

C-bus controlled TV input processor

TDA9321H

PINNING

SYMBOL

PIN

DESCRIPTION

DEC

SIF

SIF AGC decoupling

VIF1

VIF input 1

VIF2

VIF input 2

DEC

VIF

VIF AGC decoupling

QSS/AM

combined QSS and AM sound output

VIFPLL

VIF PLL ﬁlter

VIFVCO1

VIF VCO tuned circuit 1

VIFVCO2

VIF VCO tuned circuit 2

GND1

main supply ground

VIFO

VIF output

positive supply 1 (+8 V)

GDI

group delay correction input

GDO

group delay correction output

CVBS

int

internal CVBS input

AV1

AV input 1

CVBS1

CVBS input 1

AV2

AV input 2

CVBS2

CVBS input 2

SW0

switch output bit 0 (I

C-bus)

CVBS/Y3

CVBS or luminance input 3

chrominance input 3

SW1

switch output bit 1 (I

C-bus)

CVBS/Y4

CVBS or luminance input 4

chrominance input 4

SYS1

system output 1 for comb ﬁlter

CVBSCF

CVBS output for comb ﬁlter

SYS2

system output 2 for comb ﬁlter

YCF

luminance input from comb ﬁlter

CCF

chrominance input from comb ﬁlter

REFO

reference output (subcarrier)

GND2

digital supply ground

CVBSPIP

CVBS output for Picture-In-Picture

DEC

DIG

digital supply decoupling

CVBSTXT

CVBS output for teletext

DEC

band gap decoupling

RI1

red input 1

GI1

green input 1

BI1

blue input 1

RGB1

RGB insertion input 1

RGB2

RGB insertion input 2

RI2

red input 2

GI2

green input 2

BI2

blue input 2

GND3

ground 3

positive supply 2 (+8 V)

SCL

serial clock input (I

C-bus)

SDA

serial data input/output (I

C-bus)

address select input (I

C-bus)

luminance output

U-signal output

V-signal output

LFBP

loop ﬁlter burst phase detector

DEC

SEC

SECAM PLL decoupling

XTALA

crystal A (4.433619 MHz)

XTALB

crystal B (3.582056 MHz)

XTALC

crystal C (3.575611 MHz)

XTALD

crystal D (3.579545 MHz)

PH1LF

phase 1 loop ﬁlter

SCO

sandcastle pulse output

HA/CLP

horizontal pulse output or clamp pulse

input/output

vertical pulse output

TAGC

tuner AGC output

SIF1

SIF input 1

SIF2

SIF input 2

SYMBOL

PIN

DESCRIPTION

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

C-bus controlled TV input processor

TDA9321H

FUNCTIONAL DESCRIPTION

Vision IF ampliﬁer

The VIF amplifier contains 3 AC-coupled control stages

with a total gain control range which is higher than 66 dB.

The sensitivity of the circuit is comparable with that of

modern IF-ICs.

The video signal is demodulated by a PLL carrier

regenerator. This circuit contains a frequency detector and

a phase detector. During acquisition the frequency

detector will tune the VCO to the correct frequency.

The initial adjustment of the oscillator is realized via the

C-bus. The switching between SECAM L and L’ can also

be realized via the I

C-bus. After lock-in the phase

detector controls the VCO so that a stable phase

relationship between the VCO and the input signal is

achieved. The VCO operates at twice the IF frequency.

The reference signal for the demodulator is obtained by

means of a frequency divider circuit. To get a good

performance for phase modulated carrier signals the

control speed of the PLL can be increased by bit FFI.

The AFC output is obtained by using the VCO control

voltage of the PLL and can be read via the I

C-bus.

For fast search tuning systems the window of the AFC can

be increased with a factor 3. The setting is realized with

bit AFW.

The AGC detector operates on top-sync and

top-white-level. The demodulation polarity is switched via

the I

C-bus. The AGC detector time constant capacitor is

connected externally; this is mainly because of the

flexibility of the application. The time constant of the AGC

system during positive modulation is rather long, this is to

avoid visible variations of the signal amplitude. To improve

the speed of the AGC system a circuit has been included

which detects whether the AGC detector is activated every

frame period. When, during 3 field periods, no action is

detected the speed of the system is increased. For signals

without peak white information the system switches

automatically to a gated black level AGC. Because a black

level clamp pulse is required for this mode of operation the

circuit will only switch to black level AGC in the internal

mode.

The circuits contain a video identification (ident) circuit

which is independent of the synchronization circuit.

Therefore search tuning is possible when the display

section of the receiver is used as a monitor. However, this

ident circuit cannot be made as sensitive as the slower

sync ident circuit (bit SL). It is recommended to use both

ident outputs to obtain a reliable search system. The ident

output is supplied to the tuning system via the I

C-bus.

The input of the ident circuit is connected to pin 14

(see Fig.3). This has the advantage that the ident circuit

can also be made operative when a scrambled signal is

received (descrambler connected between pins 10

and 14). A second advantage is that the ident circuit can

be used when the VIF amplifier is not used (e.g. with

built-in satellite tuners). The video ident circuit can also be

used to identify the selected CBVS or Y/C signal.

The switching between the 2 modes can be realized with

bit VIM.

The TDA9321H contains a group delay correction circuit

which can be switched between the BG and a flat group

delay response characteristic. This has the advantage that

in multistandard receivers no compromise has to be made

for the choice of the SAW filter. Both the input and output

of the group delay correction circuit are externally

available so that the sound trap can be connected

between the VIF output and the group delay correction

input. The output signal of the correction circuit can be

supplied to the internal video processing circuit and to the

external SCART plug.

The IC has several (I

C-bus controlled) output ports which

can be used to switch sound traps or other external

components.

When the VIF amplifier is not used the complete VIF

amplifier can be switched off with bit IFO.

Sound circuit

The SIF amplifier is similar to the VIF amplifier and has a

gain control range of approximately 66 dB. The AGC

circuit is related to the SIF carrier levels (average level of

AM or FM carriers) and ensures a constant signal

amplitude to the AM demodulator and the QSS mixer.

The single reference QSS mixer is realized by a multiplier.

In this multiplier the SIF signal is converted to the

intercarrier frequency by mixing it with the regenerated

picture carrier from the VCO. The mixer output signal is

supplied to the output via a high-pass filter for attenuation

of the residual video signals. With this system a high

performance hi-fi stereo sound processing can be

achieved.

The AM sound demodulator is realized by a multiplier.

The modulated SIF signal is multiplied in phase with the

limited SIF signal. The demodulator output signal is

supplied to the output via a low-pass filter for attenuation

of the carrier harmonics.

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

C-bus controlled TV input processor

TDA9321H

Video switches

The circuit has 3 CVBS inputs (1 internal and 2 externals)

and 2 Y/C inputs. The Y/C inputs can also be used as

additional CVBS inputs. The switch configuration is given

in Fig.3. The various sources can be selected via the

C-bus.

The circuit can be set in a mode in which it automatically

detects whether a CVBS or a Y/C signal is supplied to the

Y/C inputs. In this mode the TV-standard identification first

takes place on the added Y/CVBS and the C input signal.

Then both chrominance input signal amplitudes are

checked once and the input signal with the highest burst

signal amplitude is selected. The result of the detection

can be read via the I

C-bus.

The IC has 2 inputs (AV1 and AV2) which can be used to

read the status levels of pin 8 of the SCART plug.

The information is available in the output status byte 02 in

bits D0 to D3.

The 3 outputs of the video switches (CVBSCF, CVBSTXT

and CVBSPIP) can be independently switched to the

various input signals. The names are just arbitrary and it is,

for instance, possible to use the CVBSCF signal to drive

the comb filter and the teletext decoder in parallel and to

supply the CVBSTXT signal to the SCART plug (via an

emitter follower).

For comb filter interfacing the circuit has the CVBSCF

output, a 3rd Y/C input, a reference signal output REFO

and 2 control pins (SYS1 and SYS2) which switch the

comb filter to the standard of the incoming signal (as

detected by the ident circuit of the colour decoder). When

a signal is recognized which can be combed and the comb

filter is enabled by bit ECMB the Y/C signals coming from

the comb filter are automatically selected. This is indicated

via bit CMB in output status byte 02 (D5). For signals

which cannot be combed (such as SECAM or

black-to-white signals) the Y/C signals coming from the

comb filter are not selected.

Chrominance and luminance processing

The circuits contain a chrominance band-pass, a SECAM

cloche filter and a chrominance trap circuit. The filters are

realized by means of gyrator circuits and they are

automatically calibrated by comparing the tuning

frequency with the crystal frequency of the decoder.

The luminance delay line is also realized by means of

gyrator circuits. The centre frequency of the chrominance

band-pass filter is switchable via the I

C-bus so that the

performance can be optimized for ‘front-end’ signals and

external CVBS signals.

The luminance output signal which is derived from the

incoming CVBS or Y/C signal can be varied in amplitude

by means of a separate gain setting control via the I

C-bus

control bits GAI1 and GAI0. The gain variation which can

be realized with these bits is

−

1 to +2 dB.

Colour decoder

The colour decoder can decode PAL, NTSC and SECAM

signals. The PAL/NTSC decoder contains an

alignment-free crystal oscillator with 4 separate pins for

crystal connection, a killer circuit and two colour difference

demodulators. The 90

phase shift for the reference signal

is produced internally.

Because it is possible to connect 4 different crystals to the

colour decoder, all colour standards can be decoded

without external switching circuits. Which crystals are

connected to the decoder must be indicated via the

C-bus. The crystal connection pins which are not used

must be left open-circuit.

The horizontal oscillator is calibrated by means of the

crystal frequency of the colour PLL. For a reliable

calibration it is very important that the crystal indication

bits XA to XD are not corrupted. For this reason

bits XA to XD can be read in the output bytes so that the

software can check the I

C-bus transmission.

The IC contains an Automatic Colour Limiting (ACL) circuit

which is switchable via the I

C-bus and prevents

oversaturation occuring when signals with a high

chrominance-to-burst ratio are received. The ACL circuit is

designed such that it only reduces the chrominance signal

and not the burst signal. This has the advantage that the

colour sensitivity is not affected by this function. The ACL

function is mainly intended for NTSC signals but it can also

be used for PAL signals. For SECAM signals the ACL

function should be switched off.

The SECAM decoder contains an auto-calibrating PLL

demodulator which has two references: the 4.43 MHz

subcarrier frequency which is obtained from the crystal

oscillator which is used to tune the PLL to the desired

free-running frequency and the band gap reference to

obtain the correct absolute value of the output signal.

The VCO of the PLL is calibrated during each vertical

blanking period, when the IC is in search or SECAM mode.

The circuit can also decode the PALplus helper signal and

can insert the various reference signals: set-ups and

timing signals which are required for the PALplus decoder

ICs.

The baseband delay line (TDA4665 function) is integrated.