DATA SHEET
Product specification
Supersedes data of 1997 Aug 21
File under Integrated Circuits, IC02
1998 Nov 03
INTEGRATED CIRCUITS
TDA8761A
9-bit analog-to-digital converter for
digital video
1998 Nov 03
2
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
FEATURES
•
9-bit resolution
•
Sampling rate up to 40 MHz
•
DC sampling allowed
•
One clock cycle conversion only
•
High signal-to-noise ratio over a large analog input
frequency range (8.2 effective bits at 10 MHz full-scale
input at f
clk
= 30 MHz)
•
No missing codes guaranteed
•
In Range (IR) CMOS output
•
Levels TTL and CMOS compatible digital inputs
•
3 to 5 V CMOS digital outputs
•
Low-level AC clock input signal allowed
•
External reference voltage regulator
•
Power dissipation only 158 mW (typical)
•
Low analog input capacitance, no buffer amplifier
required
•
No sample-and-hold circuit required.
APPLICATIONS
Analog-to-digital conversion for:
•
Video data digitizing
•
Digital Video Broadcasting (DVB)
•
Cable TV.
GENERAL DESCRIPTION
The TDA8761A is a 9-bit Analog-to-Digital Converter
(ADC) for professional video and digital video set box
applications. It converts the analog input signal into 9-bit
binary-coded digital words at a maximum sampling rate of
40 MHz. Its linearity performance ensures the required
conversion accuracy in the event of 256-QAM
demodulator concept and for all symbol frequencies.
All digital inputs and outputs are TTL and CMOS
compatible, although a low-level sine wave clock input
signal is allowed.
QUICK REFERENCE DATA
Note
1. f
i
= 10 MHz and f
clk
= 30 MHz; f
i
= 8 MHz and f
clk
= 20 MHz.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output stages supply voltage
3.0
3.3
5.25
V
I
CCA
analog supply current
−
18
24
mA
I
CCD
digital supply current
−
13
18
mA
I
CCO
output stages supply current
f
clk
= 30 MHz; ramp input
−
1
2
mA
INL
integral non-linearity
f
clk
= 30 MHz; ramp input
−
±
0.8
±
1.6
LSB
AINL
AC integral non-linearity
full-scale input sine wave; note 1
−
±
0.75
0.9
LSB
50% full-scale input sine wave; note 1
−
±
0.5
±
0.75
LSB
DNL
differential non-linearity
f
clk
= 30 MHz; ramp input
−
±
0.3
±
0.7
LSB
ADNL
AC differential non-linearity
full-scale input sine wave; note 1
−
±
0.5
±
0.75
LSB
50% full-scale input sine wave; note 1
−
±
0.3
±
0.5
LSB
f
clk(max)
maximum clock frequency
40
−
−
MHz
P
tot
total power dissipation
−
158
173
mW
1998 Nov 03
3
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
ORDERING INFORMATION
BLOCK DIAGRAM
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA8761AM
SSOP28
plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
Fig.1 Block diagram.
handbook, full pagewidth
12
DGND2
6
8
7
RLAD
9
VRB
VRM
VRT
V I
11
VCCD2
3
26
VCCA
21
22
23
24
20 D3
D4
D5
D6
D7
19
18
25
2
D2
D1
17 D0
D8
IN RANGE LATCH
CMOS
OUTPUTS
LATCHES
ANALOG -TO - DIGITAL
CONVERTER
CLOCK DRIVER
MBG910
CMOS OUTPUT
1
CLK
10
OE
TC
TDA8761A
13
VCCO
4
AGND
analog ground
digital grounds
27
DGND1
14
OGND
output ground
analog
voltage input
data outputs
LSB
MSB
28 VCCD1
IR
output
1998 Nov 03
4
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
PINNING
SYMBOL
PIN
DESCRIPTION
CLK
1
clock input
TC
2
two’s complement input (active LOW)
V
CCA
3
analog supply voltage (5 V)
AGND
4
analog ground
n.c.
5
not connected
V
RB
6
reference voltage BOTTOM input
V
RM
7
reference voltage MIDDLE
V
I
8
analog input voltage
V
RT
9
reference voltage TOP input
OE
10
output enable input (CMOS level
input, active LOW)
V
CCD2
11
digital supply voltage 2 (5 V)
DGND2
12
digital ground 2
V
CCO
13
supply voltage for output stages
(3 to 5 V)
OGND
14
output ground
n.c.
15
not connected
n.c.
16
not connected
D0
17
data output; bit 0 (LSB)
D1
18
data output; bit 1
D2
19
data output; bit 2
D3
20
data output; bit 3
D4
21
data output; bit 4
D5
22
data output; bit 5
D6
23
data output; bit 6
D7
24
data output; bit 7
D8
25
data output; bit 8 (MSB)
IR
26
in range data output
DGND1
27
digital ground 1
V
CCD1
28
digital supply voltage 1 (5 V)
Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
CLK
TC
CCA
AGND
n.c.
RB
RM
I
RT
OE
CCD2
DGND2
CCO
OGND
CCD1
DGND1
IR
D8
D7
D6
D5
D4
D3
D2
D1
D0
n.c.
n.c.
V
V
V
V
V
V
V
V
TDA8761A
MBG909
1998 Nov 03
5
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. The supply voltages V
CCA
, V
CCD
and V
CCO
may have any value between
−
0.3 and +7.0 V provided that the supply
voltage differences
∆
V
CC
are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
CCA
analog supply voltage
note 1
−
0.3
+7.0
V
V
CCD
digital supply voltage
note 1
−
0.3
+7.0
V
V
CCO
output stages supply voltage
note 1
−
0.3
+7.0
V
∆
V
CC
supply voltage differences
between
V
CCA
and V
CCD
−
1.0
+1.0
V
V
CCD
and V
CCO
−
1.0
+4.0
V
V
CCA
and V
CCO
−
1.0
+4.0
V
V
I
input voltage
referenced to AGND
−
0.3
+7.0
V
V
i(p-p)
AC input voltage for switching
(peak-to-peak value)
referenced to DGND
−
V
CCD
V
I
O
output current
−
10
mA
T
stg
storage temperature
−
55
+150
°
C
T
amb
operating ambient temperature
0
+70
°
C
T
j
junction temperature
−
+150
°
C
SYMBOL
PARAMETER
CONDITIONS
VALUE
UNIT
R
th(j-a)
thermal resistance from junction to ambient
in free air
110
K/W
1998 Nov 03
6
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
CHARACTERISTICS
V
CCA
= V
3
to V
4
= 4.75 to 5.25 V; V
CCD
= V
11
to V
12
and V
28
to V
27
= 4.75 to 5.25 V; V
CCO
= V
13
to V
14
= 3.0 to 5.25 V;
AGND and DGND shorted together; T
amb
= 0 to 70
°
C; typical values measured at V
CCA
= V
CCD
= 5 V and
V
CCO
= 3.3 V; V
i(p-p)
= 1.8 V; C
L
= 15 pF and T
amb
= 25
°
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
CCA
analog supply voltage
4.75
5.0
5.25
V
V
CCD
digital supply voltage
4.75
5.0
5.25
V
V
CCO
output stages supply voltage
3.0
3.3
5.25
V
∆
V
CC
supply voltage differences
between
V
CCA
and V
CCD
−
0.2
−
+0.2
V
V
CCA
and V
CCO
−
0.2
−
+2.25
V
V
CCD
and V
CCO
−
0.2
−
+2.25
V
I
CCA
analog supply current
−
18
24
mA
I
CCD
digital supply current
−
13
18
mA
I
CCO
output stages supply current
f
clk
= 30 MHz; ramp input
−
1
2
mA
Inputs
C
LOCK INPUT
CLK (
REFERENCED TO
DGND); note 1
V
IL
LOW-level input voltage
0
−
0.8
V
V
IH
HIGH-level input voltage
2
−
V
CCD
V
I
IL
LOW-level input current
V
clk
= 0.8 V
−
1
0
+1
µ
A
I
IH
HIGH-level input current
V
clk
= 2 V
−
2
10
µ
A
Z
i
input impedance
f
clk
= 30 MHz
−
2
−
k
Ω
C
i
input capacitance
−
2
−
pF
I
NPUTS
OE
AND
TC (
REFERENCED TO
DGND); see Table 2
V
IL
LOW-level input voltage
0
−
0.8
V
V
IH
HIGH-level input voltage
2
−
V
CCD
V
I
IL
LOW-level input current
V
IL
= 0.8 V
−
1
−
−
µ
A
I
IH
HIGH-level input current
V
IH
= 2.0 V
−
−
1
µ
A
V
I
(
ANALOG INPUT VOLTAGE REFERENCED TO
AGND)
I
IL
LOW-level input current
V
I
= V
RB
= 1.3 V
−
17
−
µ
A
I
IH
HIGH-level input current
V
I
= V
RT
= 3.43 V
−
35
−
µ
A
Z
i
input impedance
f
i
= 10 MHz
−
8
−
k
Ω
C
i
input capacitance
−
5
−
pF
1998 Nov 03
7
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
Reference voltages for the resistor ladder; see Table 1
V
RB
reference voltage BOTTOM
1.2
1.3
2.45
V
V
RT
reference voltage TOP
3.2
3.43
V
CCA
−
0.8 V
V
diff
differential reference voltage
V
RT
−
V
RB
2
2.13
3.0
V
I
ref
reference current
V
RT
−
V
RB
= 2.13 V
−
8.7
−
mA
R
LAD
resistor ladder
−
245
−
Ω
TC
RLAD
temperature coefficient of the
resistor ladder
−
1860
−
ppm
−
456
−
m
Ω
/K
V
osB
offset voltage BOTTOM
note 2
−
160
−
mV
V
osT
offset voltage TOP
note 2
−
160
−
mV
V
i(p-p)
analog input voltage
(peak-to-peak value)
note 3
1.7
1.81
2.55
V
Outputs
D
IGITAL OUTPUTS
D8
TO
D0
AND
IR (
REFERENCED TO
OGND)
V
OL
LOW-level output voltage
I
OL
= 1 mA
0
−
0.5
V
V
OH
HIGH-level output voltage
I
OH
=
−
1 mA
V
CCO
−
0.5
−
V
CCO
V
I
OZ
output current in 3-state mode
0.5 V < V
O
< V
CCO
−
20
−
+20
µ
A
Switching characteristics
C
LOCK INPUT
CLK; see Fig.4; note 1
f
clk(max)
maximum clock frequency
40
−
−
MHz
t
CPH
clock pulse width HIGH
10
−
−
ns
t
CPL
clock pulse width LOW
10
−
−
ns
Analog signal processing
L
INEARITY
INL
integral non-linearity
f
clk
= 30 MHz; ramp input
−
±
0.4
±
1
LSB
AINL
AC integral non-linearity
full-scale input sine
wave; note 4
−
±
0.75
±
0.9
LSB
50% full-scale input sine
wave; note 4
−
±
0.5
±
0.75
LSB
DNL
differential non-linearity
f
clk
= 30 MHz; ramp input
−
±
0.3
±
0.7
LSB
ADNL
AC differential non-linearity
full-scale input sine
wave; note 4
−
±
0.5
±
0.75
LSB
50% full-scale input sine
wave; note 4
−
±
0.3
±
0.5
LSB
OFER
offset error
middle code;
V
RB
= 1.3 V;
V
RT
= 3.43 V
−
±
1
−
LSB
GER
gain error (from
device to device)
V
RB
= 1.3 V;
V
RT
= 3.43 V; note 5
−
±
0.1
−
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
1998 Nov 03
8
Philips Semiconductors
Product specification
9-bit analog-to-digital converter
for digital video
TDA8761A
B
ANDWIDTH
(f
clk
= 30 MH
Z
)
B
analog bandwidth
full-scale sine wave;
note 6
−
15
−
MHz
75% full-scale sine wave;
note 6
−
20
−
MHz
small signal at mid-scale;
V
I
=
±
10 LSB at
code 256; note 6
−
350
−
MHz
t
STLH
analog input settling time
LOW-to-HIGH
full-scale square wave;
Fig.6; note 7
−
1.5
3.0
ns
t
STHL
analog input settling time
HIGH-to-LOW
full-scale square wave;
Fig.6; note 7
−
1.5
3.0
ns
H
ARMONICS
(f
clk
= 30 MH
Z
); see Figs 7 and 8
THD
total harmonic distortion
f
i
= 10 MHz
−
−
56
−
dB
S
IGNAL
-
TO
-
NOISE RATIO
; see Figs 7 and 8; note 8
SNR
signal-to-noise ratio (full scale)
without harmonics;
f
clk
= 30 MHz;
f
i
= 10 MHz
53
55
−
dB
E
FFECTIVE BITS
; see Figs 7 and 8; note 8
ENOB
effective bits
f
clk
= 30 MHz
f
i
= 4.43 MHz
−