DATA SHEET
Preliminary specification
File under Integrated Circuits, IC01
1999 May 10
INTEGRATED CIRCUITS
UDA1325
Universal Serial Bus (USB) CODEC
1999 May 10
2
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
FEATURES
General
•
High Quality USB-compliant Audio/HID device
•
Supports 12 Mbits/s serial data transmission
•
Fully USB Plug and Play operation
•
Supports ‘Bus-powered’ and ‘Self-powered’ operation
•
3.3 V power supply
•
Low power consumption with optional efficient power
control
•
On-chip clock oscillator, only an external crystal is
required.
Audio playback channel
•
One isochronous output endpoint
•
Supports multiple audio data formats (8, 16 and 24 bits)
•
Adaptive sample frequency support from 5 to 55 kHz
•
One master 20-bit I
2
S digital stereo playback output,
I
2
S and LSB justified serial formats
•
One slave 20-bit I
2
S digital stereo playback input,
I
2
S and LSB justified serial formats
•
Selectable volume control for left and right channel
•
Soft mute control
•
Digital bass and treble tone control
•
Selectable on-chip digital de-emphasis
•
Low total harmonic distortion (typical 90 dB)
•
High signal-to-noise ratio (typical 95 dB)
•
One stereo Line output.
Audio recording channel
•
One isochronous input endpoint
•
Supports multiple audio data formats (8, 16 and 24 bits)
•
Twelve selectable sample rates (4, 8, 16 or 32 kHz;
5.5125, 11.025, 22.05 or 44.1 kHz; 6, 12, 24 or 48 kHz)
via analog PLL (APLL).
•
Selectable sample rate between 5 to 55 kHz via a
second oscillator (optional)
•
One slave 20-bit I
2
S digital stereo recording input,
I
2
S and LSB justified serial formats
•
Programmable Gain Amplifier for left and right channel
•
Low total harmonic distortion (typical 85 dB)
•
High signal-to-noise ratio (typical 90 dB)
•
One stereo Line/Microphone input.
USB endpoints
•
2 control endpoints
•
2 interrupt endpoints
•
1 isochronous data sink endpoint
•
1 isochronous data source endpoint.
Document references
•
“USB Specification”
•
“USB Device Class Definition for Audio Devices”
•
“Device Class Definition for Human Interface Devices
(HID)”
•
“USB HID Usage Table”.
•
“USB Common Class Specification”.
1999 May 10
3
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
APPLICATIONS
•
USB monitors
•
USB speakers
•
USB microphones
•
USB headsets
•
USB telephone/answering machines
•
USB links in consumer audio devices.
GENERAL DESCRIPTION
The UDA1325 is a single chip stereo USB codec
incorporating bitstream converters designed for
implementation in USB-compliant audio peripherals and
multimedia audio applications. It contains a USB interface,
an embedded microcontroller, an Analog-to-Digital
Interface (ADIF) and an Asynchronous Digital-to-Analog
Converter (ADAC).
The USB interface consists of an analog front-end and a
USB processor. The analog front-end transforms the
differential USB data into a digital data stream. The USB
processor buffers the incoming and outgoing data from the
analog front-end and handles all low-level USB protocols.
The USB processor selects the relevant data from the
universal serial bus, performs an extensive error detection
and separates control information and audio information.
The control information is made accessible to the
microcontroller. At playback, the audio information
becomes available at the digital I
2
S output of the digital I/O
module or is fed directly to the ADAC. At recording, the
audio information is delivered by the ADIF or by the digital
I
2
S input of the I
2
S-bus interface.
All I
2
S inputs and I
2
S outputs support standard I
2
S-bus
format and the LSB justified serial data format with word
lengths of 16, 18 and 20 bits.
Via the digital I/O module with its I
2
S input and output, an
external DSP can be used for adding extra sound
processing features for the audio playback channel.
The microcontroller is responsible for handling the
high-level USB protocols, translating the incoming control
requests and managing the user interface via general
purpose pins and an I
2
C-bus.
The ADAC enables the wide and continuous range of
playback sampling frequencies. By means of a Sample
Frequency Generator (SFG), the ADAC is able to
reconstruct the average sample frequency from the
incoming audio samples. The ADAC also performs the
playback sound processing. The ADAC consists of a
FIFO, an unique audio feature processing DSP, the SFG,
digital filters, a variable hold register, a Noise Shaper (NS)
and a Filter Stream DAC (FSDAC) with line output drivers.
The audio information is applied to the ADAC via the USB
processor or via the digital I
2
S input of the digital I/O
module.
The ADIF consists of an Programmable Gain Amplifier
(PGA), an Analog-to-Digital Converter (ADC) and a
Decimator Filter (DF). An Analog Phase Lock Loop (APLL)
or oscillator is used for creating the clock signal of the
ADIF. The clock frequency for the ADIF can be controlled
via the microcontroller. Several clock frequencies are
possible for sampling the analog input signal at different
sampling rates.
The wide dynamic range of the bitstream conversion
technique used in the UDA1325 for both the playback and
recording channel guarantees a high audio sound quality.
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UDA1325PS
SDIP42
plastic shrink dual in-line package; 42 leads (600 mil)
SOT270-1
UDA1325H
QFP64
plastic quad flat package; 64 leads (lead length 1.95 mm);
body 14
×
20
×
2.8 mm
SOT319-2
1999 May 10
4
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
QUICK REFERENCE DATA
Note
1. Exclusive the IDDE current which depends on the components connected to the I/O pins.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DDE
supply voltage periphery
4.75
5.0
5.25
V
V
DDI
supply voltage core
3.0
3.3
3.6
V
I
DD(tot)
total supply current
−
60
tbf
mA
I
DD(tot)(ps)
total supply current in power-saving
mode
note 1
−
360
−
µ
A
Dynamic performance DAC
(THD + N)/S
total harmonic distortion plus
noise-to-signal ratio
f
s
= 44.1 kHz; R
L
= 5 k
Ω
f
i
= 1 kHz (0 dB)
−
−
90
−
80
dB
−
0.0032
0.01
%
f
i
= 1 kHz (
−
60 dB)
−
−
30
−
20
dB
−
3.2
10
%
S/N
signal-to-noise ratio at bipolar zero
A-weighted at code 0000H 90
95
−
dBA
V
o(FS)(rms)
full-scale output voltage
(RMS value)
V
DD
= 3.3 V
−
0.66
−
V
Dynamic performance PGA and ADC
(THD + N)/S
total harmonic distortion plus
noise-to-signal ratio
f
s
= 44.1 kHz;
PGA gain = 0 dB
f
i
= 1 kHz; (0 dB);
V
i
= 1.0 V (RMS)
−
−
85
−
80
dB
−
0.0056
0.01
%
f
i
= 1 kHz (
−
60 dB)
−
−
30
−
20
dB
−
3.2
10.0
%
S/N
signal-to-noise ratio
V
i
= 0.0 V
90
95
−
dBA
General characteristics
f
i(s)
audio input sample frequency
5
−
55
kHz
T
amb
operating ambient temperature
0
25
70
°
C
1999 May 10
5
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
BLOCK DIAGRAM
Fig.1 Block diagram (QFP64 package).
handbook, full pagewidth
MGM108
TIMING
ANALOG
PLL
OSC
48 MHz
OSC
ADC
24 (19)
27
25 (20)
26 (21)
28 (22)
52 (39)
53 (40)
54 (41)
55 (42)
63 (4)
1 (5)
2 (6)
13 (14)
17 (16)
15 (15)
(12) 11
(13) 12
(10) 9
(11) 10
(23) 32
(24) 33
(29) 38
(30) 39
(33) 42
(35) 44
ANALOG FRONT-END
USB-PROCESSOR
DIGITAL I/O
FIFO
AUDIO FEATURE
PROCESSING DSP
UPSAMPLE FILTERS
VARIABLE HOLD REGISTER
3rd-ORDER NOISE SHAPER
REFERENCE VOLTAGE
57 (1)
59 (2)
61 (3)
43 (34)
47 (36)
8 (9)
6 (8)
MICRO-
CONTROLLER
TEST
CONTROL
BLOCK
SAMPLE
FREQUENCY
GENERATOR
MUX
I
2
S-BUS
INTERFACE
DECIMATOR
FILTER
PGA
LEFT
Σ∆
ADC
PGA
RIGHT
Σ∆
ADC
LEFT
DAC
RIGHT
DAC
49 (37)
51 (38)
45, 46
41 (32)
40 (31)
Vref(AD)
Vref(DA)
(28) 37
(25) 34
(27) 36
(26) 35
(7) 4
(18) 21
(17) 19
n.c.
UDA1325
+
−
−
+
VRN
VINR
VSSA2
VINL
VSSA1
VDDA1
VOUTR
RTCB
GP4/BCKO
SHTCB
D
−
7, 5, 3, 64,
62, 60, 58, 56
P0.7 to P0.0
14, 16, 18, 20,
22, 23, 29, 30
P2.0 to P2.7
D
+
VDDI
VSSI
VDDE
GP1/DI
GP0/BCKI
VDDA2
BCK
48
EA
50
ALE
WS
DA
31
PSEN
VSSA3
XTAL2a
VDDA3
VRP
GP2/DO
GP3/WSO
XTAL1a
SDA
VSSX
XTAL1b
XTAL2b
CLK
VDDX
VSSO
VOUTL
TC
SCL
VDDO
VSSE
GP5/WSI
The pin numbers given in parenthesis refer to the SDIP42 version.
1999 May 10
6
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
PINNING
SYMBOL
PIN
QFP64
PIN
SDIP42
I/O
DESCRIPTION
GP3/WSO
1
5
I/O
general purpose pin 3 or word select output
GP4/BCKO
2
6
I/O
general purpose pin 4 or bit clock output
P0.5
3
−
I/O
Port 0.5 of the microcontroller
SHTCB
4
7
I
shift clock of the test control block (active HIGH)
P0.6
5
−
I/O
Port 0.6 of the microcontroller
D
−
6
8
I/O
negative data line of the differential data bus, conforms to the USB
standard
P0.7
7
−
I/O
Port 0.7 of the microcontroller
D+
8
9
I/O
positive data line of the differential data bus, conforms to the USB
standard
V
DDI
9
10
−
digital supply voltage for core
V
SSI
10
11
−
digital ground for core
V
SSE
11
12
−
digital ground for I/O pads
V
DDE
12
13
−
digital supply voltage for I/O pads
GP1/DI
13
14
I/O
general purpose pin 1 or data input
P2.0
14
−
I/O
Port 2.0 of the microcontroller
GP5/WSI
15
15
I/O
general purpose pin 5 or word select input
P2.1
16
−
I/O
Port 2.1 of the microcontroller
GP0/BCKI
17
16
I/O
general purpose pin 0 or bit clock input
P2.2
18
−
I/O
Port 2.2 of the microcontroller
SCL
19
17
I/O
serial clock line I
2
C-bus
P2.3
20
−
I/O
Port 2.3 of the microcontroller
SDA
21
18
I/O
serial data line I
2
C-bus
P2.4
22
−
I/O
Port 2.4 of the microcontroller
P2.5
23
−
I/O
Port 2.5 of the microcontroller
V
SSX
24
19
−
crystal oscillator ground (48 MHz)
XTAL1b
25
20
I
crystal input (analog; 48 MHz)
XTAL2b
26
21
O
crystal output (analog; 48 MHz)
CLK
27
−
O
48 MHz clock output signal
V
DDX
28
22
−
supply crystal oscillator (48 MHz)
P2.6
29
−
I/O
Port 2.6 of the microcontroller
P2.7
30
−
I/O
Port 2.7 of the microcontroller
PSEN
31
−
I/O
program store enable (active LOW)
V
DDO
32
23
−
supply voltage for operational amplifier
V
SSO
33
24
−
operational amplifier ground
VOUTL
34
25
O
voltage output left channel
TC
35
26
I
test control input (active HIGH)
RTCB
36
27
I
asynchronous reset input of the test control block (active HIGH)
VOUTR
37
28
O
voltage output right channel
1999 May 10
7
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
V
DDA1
38
29
−
analog supply voltage 1
V
SSA1
39
30
−
analog ground 1
V
ref(DA)
40
31
O
reference voltage output DAC
V
ref(AD)
41
32
O
reference voltage output ADC
V
DDA2
42
33
−
analog supply voltage 2
VINL
43
34
I
input signal left channel PGA
V
SSA2
44
35
−
analog ground 2
n.c.
45
−
−
not connected
n.c.
46
−
−
not connected
VINR
47
36
I
input signal right channel PGA
EA
48
−
−
external access (active LOW)
VRN
49
37
I
negative reference input voltage ADC
ALE
50
−
−
address latch enable (active HIGH)
VRP
51
38
I
positive reference input voltage ADC
V
DDA3
52
39
−
supply voltage for crystal oscillator and analog PLL
XTAL2a
53
40
O
crystal output (analog; ADC)
XTAL1a
54
41
I
crystal input (analog; ADC)
V
SSA3
55
42
−
crystal oscillator and analog PLL ground
P0.0
56
−
I/O
Port 0.0 of the microcontroller
DA
57
1
I
data Input (digital)
P0.1
58
−
I/O
Port 0.1 of the microcontroller
WS
59
2
I
word select Input (digital)
P0.2
60
−
I/O
Port 0.2 of the microcontroller
BCK
61
3
I
bit clock Input (digital)
P0.3
62
−
I/O
Port 0.3 of the microcontroller
GP2/DO
63
4
I/O
general purpose pin 2 or data output
P0.4
64
−
I/O
Port 0.4 of the microcontroller
SYMBOL
PIN
QFP64
PIN
SDIP42
I/O
DESCRIPTION
1999 May 10
8
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Fig.2 Pin configuration (QFP64 package).
handbook, full pagewidth
UDA1325H
MGL349
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GP3/WSO
GP4/BCKO
P0.5
SHTCB
P0.6
D
−
P0.7
D
+
VDDI
VSSI
VSSE
VDDE
GP1/DI
P2.0
GP5/WSI
P2.1
GP0/BCKI
P2.2
SCL
VRP
ALE
VRN
EA
VINR
n.c.
n.c.
VSSA2
VINL
VDDA2
Vref(AD)
Vref(DA)
VSSA1
VDDA1
VOUTR
RTCB
TC
VOUTL
VSSO
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
P0.4
GP2/DO
P0.3
BCK
P0.2
WS
P0.1
DA
P0.0
V
SSA3
XTAL1a
XTAL2a
V
DDA3
P2.3
SDA
P2.4
P2.5
V
SSX
XTAL1b
XTAL2b
CLK
V
DDX
P2.6
P2.7
PSEN
V
DDO
1999 May 10
9
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB) CODEC
UDA1325
Fig.3 Pin configuration (SDIP42 package).
handbook, halfpage
UDA1325
MGM106
1
2
42
41
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSSA3
XTAL1a
XTAL2a
VDDA3
VRP
VRN
VINR
VSSA2
VINL
VDDA2
Vref(AD)
Vref(DA)
VSSA1
VDDA1
VOUTR
RTCB
TC
VOUTL
VSSO
VDDO
VDDX
DA
WS
BCK
GP2/DO
GP3/WSO
GP4/BCKO
SHTCB
D
−
D
+
VDDI
VSSI
VSSE
VDDE
GP1/DI
GP5/WSI
GP0/BCKI
SCL
SDA
VSSX
XTAL1b
XTAL2b
FUNCTIONAL DESCRIPTION
The Universal Serial Bus (USB)
Data and power is transferred via the USB over a 4-wire
cable. The signalling occurs over two wires and
point-to-point segments. The signals on each segment are
differentially driven into a cable of 90
Ω
intrinsic
impedance. The differential receiver features input
sensitivity of at least 200 mV and sufficient common mode
rejection.
The analog front-end
The analog front-end is an on-chip generic USB
transceiver. It is designed to allow voltage levels up to V
DD
from standard or programmable logic to interface with the
physical layer of the USB. It is capable of receiving and
transmitting serial data at full speed (12 Mbits/s).
The USB processor
The USB processor forms the interface between the
analog front-end, the ADIF, the ADAC and the
microcontroller. The USB processor consists of:
•
A bit clock recovery circuit
•
The Philips Serial Interface Engine (PSIE)
•
The Memory Management Unit (MMU)
•
The Audio Sample Redistribution (ASR) module.
Bit clock recovery
The bit clock recovery circuit recovers the clock from the
incoming USB data stream using four times over-sampling
principle. It is able to track jitter and frequency drift
specified by the USB specification.
Philips Serial Interface Engine (PSIE)
The Philips SIE implements the full USB protocol layer.
It translates the electrical USB signals into data bytes and
control signals. Depending upon the USB device address
and the USB endpoint address, the USB data is directed
to the correct endpoint buffer. The data transfer could be
of bulk, isochronous, control or interrupt type.
The functions of the PSIE include: synchronization pattern
recognition, parallel/serial conversion, bit
stuffing/de-stuffing, CRC checking/generation, PID
verification/generation, address recognition and
handshake evaluation/generation.
The amount of bytes/packet on all endpoints is limited by
the PSIE hardware to 8 bytes/packet, except for both