1
April 1998
ML4812
*
Power Factor Controller
GENERAL DESCRIPTION
The ML4812 is designed to optimally facilitate a peak
current control boost type power factor correction system.
Special care has been taken in the design of the ML4812
to increase system noise immunity. The circuit includes a
precision reference, gain modulator, error amplifier, over-
voltage protection, ramp compensation, as well as a high
current output. In addition, start-up is simplified by an
under-voltage lockout circuit with 6V hysteresis.
In a typical application, the ML4812 functions as a
current mode regulator. The current which is necessary to
terminate the cycle is a product of the sinusoidal line
voltage times the output of the error amplifier which is
regulating the output DC voltage. Ramp compensation is
programmable with an external resistor, to provide stable
operation when the duty cycle exceeds 50%.
BLOCK DIAGRAM
(Pin Configuration Shown is for DIP Version)
FEATURES
s
Precision buffered 5V reference (±0.5%)
s
Current-input gain modulator reduces external
components and improves noise immunity
s
Programmable ramp compensation circuit
s
1A peak current totem-pole output drive
s
Overvoltage comparator helps prevent output
voltage “runaway”
s
Wide common mode range in current sense
comparators for better noise immunity
s
Large oscillator amplitude for better noise immunity
5V
OVP
ISENSE
GM OUT
EA OUT
ISINE
RAMP COMP
CT
RT
ERROR
AMP
IEA
OSC
1k
Ω
UNDER
VOLTAGE
LOCKOUT
SHDN
OUT
PWR GND
VREF
VCC
GND
CLOCK
VCC
EA–
32V
5
1
2
10
12
11
14
13
15
9
3
4
6
7
16
8
+
–
5V
+
–
5V
+
–
–
5V
S
R
Q
Q
GAIN MODULATOR
* Some Packages Are End Of Life
ML4812
2
PIN CONFIGURATION
PIN
NAME
FUNCTION
1
I
SENSE
Input from the current sense
transformer to the non-inverting input
of the PWM comparator.
2
GM OUT
Output of gain modulator.
A resistor to ground on this pin
converts the current to a voltage.
This pin is clamped to 5V and tied
to the inverting input of the PWM
comparator.
3
EA OUT
Output of error amplifier.
4
EA–
Inverting input to error amplifier.
5
OVP
Input to over voltage comparator.
6
I
SINE
Current gain modulator input.
7
RAMP
COMP
Buffered output from the oscillator
ramp (C
T
). A resistor to ground sets the
current which is internally subtracted
from the product of I
SINE
and I
EA
in
the gain modulator.
PIN
NAME
FUNCTION
8
R
T
Oscillator timing resistor pin. A 5V
source sets a current in the external
resistor which is mirrored to charge
C
T
.
9
CLOCK
Digital clock output.
10
SHDN
A TTL compatible low level on this
pin turns off the output.
11
PWR GND Return for the high current totem pole
output.
12
OUT
High current totem pole output.
13
V
CC
Positive Supply for the IC.
14
V
REF
Buffered output for the 5V voltage
reference.
15
GND
Analog signal ground.
16
C
T
Timing capacitor for the oscillator.
PIN DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ISENSE
GM OUT
EA OUT
EA–
OVP
ISINE
RAMP COMP
RT
CT
GND
VREF
VCC
OUT
PWR GND
SHDN
CLOCK
TOP VIEW
ML4812
16-Pin PDIP (P16)
TOP VIEW
ML4812
20-Pin PLCC (Q20)
EA OUT
EA–
NC
OVP
ISINE
VREF
VCC
NC
OUT
PWR GND
GM OUT
I SENSE
NC
C
T
GND
RAMP COMP
R
T
NC
CLOCK
SHDN
4
5
6
7
8
18
17
16
15
14
3
2
1 20 19
9 10 11 12 13
ML4812
3
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.
Supply Current (I
CC
) ............................................... 30mA
Output Current Source or Sink (OUT) DC ................ 1.0A
Output Energy (capacitive load per cycle) .................. 5µJ
Gain Modulator I
SINE
Input (I
SINE
) ......................... 1.2mA
Error Amp Sink Current (EA OUT) .......................... 10mA
Oscillator Charge Current ........................................ 2mA
Analog Inputs (I
SENSE
, EA–, OVP) .............. –0.3V to 5.5V
Junction Temperature ............................................. 150°C
Storage Temperature Range ..................... –65°C to 150°C
Lead Temperature (soldering 10 sec.) ..................... 260°C
Thermal Resistance (
θ
JA
)
20-Pin PLCC .................................................... 60°C/W
16-Pin PDIP ..................................................... 65°C/W
OPERATING CONDITIONS
Temperature Range
ML4812CX ............................................... 0°C to 70°C
ML4812IX ............................................. –40°C to 85°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
CC
= 15V , R
T
= 14k
Ω
, C
T
= 1000pF, T
A
= Operating Temperature Range (Notes 1, 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
Initial Accuracy
T
J
= 25°C
91
98
105
kHz
Voltage Stability
12V < V
CC
< 18V
0.3
%
Temperature Stability
2
%
Total Variation
Line, temperature
90
108
kHz
Ramp Valley to Peak
3.3
V
R
T
Voltage
4.8
5.0
5.2
V
Discharge Current (R
T
open)
T
J
= 25°C, V
CT
= 2V
7.8
8.4
9.0
mA
V
CT
= 2V
7.3
8.4
9.3
mA
Clock Out Voltage Low
R
L
= 16k
Ω
0.2
0.5
V
Clock Out Voltage High
R
L
= 16k
Ω
3.0
3.5
V
REFERENCE
Output Voltage
T
J
= 25°C, I
O
= 1mA
4.95
5.00
5.05
V
Line Regulation
12V < V
CC
< 25V
2
20
mV
Load Regulation
1mA < I
O
< 20mA
2
20
mV
Temperature Stability
0.4
%
Total Variation
Line, load, temp.
4.9
5.1
V
Output Noise Voltage
10Hz to 10kHz
50
µV
Long Term Stability
T
J
= 125°C, 1000 hours
5
25
mV
Short Circuit Current
V
REF
= 0V
–30
–85
–180
mA
ERROR AMPLIFIER
Input Offset Voltage
±15
mV
Input Bias Current
–0.1
–1.0
µA
Open Loop Gain
1 < V
EA OUT
< 5V
60
75
dB
PSRR
12V < V
CC
< 25V
60
75
dB
Output Sink Current
V
EA OUT
= 1.1V, V
EA–
= 6.2V
2
12
mA
Output Source Current
V
EA OUT
= 5.0V, V
EA–
= 4.8V
–0.5
–1.0
mA
Output High Voltage
I
EA OUT
= –0.5mA, V
EA–
= 4.8V
5.3
5.5
V
Output Low Voltage
I
EA OUT
= 1mA, V
EA–
= 6.2V
0.5
1.0
V
Unity Gain Bandwidth
1.0
MHz
ML4812
4
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER CONDITIONS MIN TYP MAX UNITS
GAIN MODULATOR
I
SINE
Input Voltage I
SINE
= 500µA 0.4 0.7 0.9 V
Output Current (GM OUT) I
SINE
= 500µA, EA– = V
REF
–20mV 430 470 510 µA
I
SINE
= 500µA, EA– = V
REF
+ 20mV 3 10 µA
I
SINE
= 1mA, EA– = V
REF
– 20mV 860 940 1020 µA
I
SINE
= 500µA, EA– = V
REF
– 20mV, 455 µA
I
RAMP COMP
= 50µA
Bandwidth 200 kHz
PSRR 12V < V
CC
< 25V 70 dB
OVP COMPARATOR
Input Offset Voltage Output Off –25 +5 mV
Hysteresis Output On 95 105 115 mV
Input Bias Current –0.3 –3 µA
Propagation Delay 150 ns
PWM COMPARATOR: I
SENSE
Input Offset Voltage ±15 mV
Input Offset Current ±1 µA
Input Common Mode Range –0.2 5.5 V
Input Bias Current –2 –10 µA
Propagation Delay 150 ns
I
LIMIT
Trip Point V
GM OUT
= 5.5V 4.8 5 5.2 V
OUTPUT
Output Voltage Low I
OUT
= –20mA 0.1 0.4 V
I
OUT
= –200mA 1.6 2.2 V
Output Voltage High I
OUT
= 20mA 13 13.5 V
I
OUT
= 200mA 12 13.4 V
Output Voltage Low in UVLO I
OUT
= –5mA, V
CC
= 8V 0.1 0.8 V
Output Rise/Fall Time C
L
= 1000pF 50 ns
Shutdown V
IH
2.0 V
V
IL
0.8 V
I
IL
, V
SHDN
= 0V –1.5 mA
I
IH
, V
SHDN
= 5V 10 µA
UNDER-VOLTAGE LOCKOUT
Startup Threshold 15 16 17 V
Shutdown Threshold 9 10 11 V
V
REF
Good Threshold 4.4 V
SUPPLY
Supply Current Start-Up, V
CC
= 14V, T
J
= 25°C 0.8 1.2 mA
Operating, T
J
= 25°C 20 25 mA
Internal Shunt Zener Voltage I
CC
= 30mA 25 30 34 V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: V
CC
is raised above the Startup Threshold first to activate the IC, then returned to 15V.
ML4812
5
FUNCTIONAL DESCRIPTION
OSCILLATOR
The ML4812 oscillator charges the external capacitor (C
T
)
with a current (I
SET
) equal to 5/R
SET
. When the capacitor
voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
Q2 provides a high pulse.
The Oscillator period can be described by the following
relationship:
Figure 2. Oscillator Timing Resistance vs. Frequency
Figure 1. Oscillator Block Diagram
Figure 3. Output Saturation Voltage vs. Output Current
10
SYNC
Q
2
Q
1
9
RT
16
CT
EXTERNAL
CLOCK
+
-
5.6V
ISET
8.4mA
CT
RT
ISET
CSYNC
RSYNC
CLOCK
tD
RAMP VALLEY
RAMP PEAK
V(CT)
10
R
T
(k
Ω
)
OSCILLATOR FREQUENCY (kHz)
10
100
1000
8
5
3
2
1
MAXIMUM DUTY CYCLE (%)
10nF
20nF
5nF
2nF
1nF
85%
80%
70%
90%
15
14
13
3
2
1
0
OUTPUT SA
TURA
TION
V
O
LT
A
GE (V)
OUTPUT CURRENT (mA)
0
200
400
800
600
VCC
VCC = 15V
80µs PULSED LOAD
120Hz RATE
GND
SOURCE SATURATION
LOAD TO GROUND
SINK SATURATION
LOAD TO VCC
T
T
T
OSC
RAMP
DEADTIME
=
+
where:
V
V
D
OUT
IN
ON
=
-
1
and:
T
C
V
mA I
DEADTIME
T
RAMP VALLEY TO PEAK
SET
=
´
-
8 4
.
ML4812
6
OUTPUT DRIVER STAGE
The ML4812 output driver is a 1A peak output high speed
totem pole circuit designed to quickly drive capacitive
loads, such as power MOSFET gates. (Figure 3)
ERROR AMPLIFIER
The ML4812 error amplifier is a high open loop gain,
wide bandwidth, amplifier.(Figures 4-5)
GAIN MODULATOR
The ML4812 gain modulator is of the current-input type
to provide high immunity to the disturbances caused by
high power switching. The rectified line input sine wave is
converted to a current via a dropping resistor. In this way,
small amounts of ground noise produce an insignificant
effect on the reference to the PWM comparator. The
output of the gain modulator is a current of the form: I
OUT
is proportional to I
SINE
×
I
EA,
where I
SINE
is the current in
the dropping resistor, and I
EA
is a current proportional to
FUNCTIONAL DESCRIPTION
(Continued)
Figure 5. Error Amplifier Open-Loop Gain and
Phase vs Frequency
Figure 7. Gain Modulator Linearity
5V
EA–
4
3
–
+
8V
0.5mA
EA OUT
Figure 4. Error Amplifier Configuration
the output of the error amplifier. When the error amplifier
is saturated high, the output of the gain modulator is
approximately equal to the I
SINE
input current. The gain
modulator output current is converted into the reference
voltage for the PWM comparator through a resistor to
ground on the gain modulator output. The gain modulator
output is clamped to 5V to provide current limiting.
Ramp compensation is accomplished by subtracting 1/2
of the current flowing out of RAMP COMP through a
buffer transistor driven by C
T
which is set by an external
resistor.
UNDER VOLTAGE LOCKOUT
On power-up the ML4812 remains in the UVLO
condition; output low and quiescent current low. The IC
becomes operational when V
CC
reaches 16V. When V
CC
drops below 10V, the UVLO condition is imposed.
During the UVLO condition, the 5V V
REF
pin is “off”,
making it usable as a “flag” for starting up a downstream
PWM converter.
6
2
7
16
CT
RAMP COMP
GM OUT
ISINE
ERROR CURRENT
9V
5V
IRAMP COMP
ISINE
×
ERROR CURRENT
– IRAMP COMP/2
Figure 6. Gain Modulator Block Diagram
500
400
300
200
100
0
MUL
TIPLE OUTPUT CURRENT (µA)
ERROR
AMP OUTPUT
V
O
LT
A
G
E (V)
SINE INPUT CURRENT (µA)
0
200
300
500
400
100
4.5
4.0
3.5
3.0
2.5
2.0
1.5
A
VO
L, OPEN LOOP GAIN (dB)
FREQUENCY (Hz)
10
1k
1M
100
10k
10M
100k
100
80
60
40
20
0
-20
EXCESS PHASE (degr
ees)
0
-30
-60
-90
-120
-150
-180
GAIN
PHASE
ML4812
7
ENABLE
VREF
VREF
GEN.
9V
INTERNAL
BIAS
5V VREF
VCC
–
+
I CC
(mA)
VCC (V)
0
30
20
40
10
25
20
15
10
5
0
25
20
15
10
5
0
SUPPL
Y CURRENT (mA)
TEMPERATURE (degrees)
–60
20
60
140
100
–20
–40
40
80
120
0
OPERATING CURRENT
STARTUP
∆
V
REF
(mV)
IREF (mA)
0
40
100
20
60
120
80
0
-4
-8
-12
-16
-20
-24
Figure 10. Reference Load Regulation
Figure 8. Under-Voltage Lockout Block Diagram
Figure 9a. Total Supply Current vs. Supply Voltage
Figure 9b. Supply Current (I
CC
) vs. Temperature
TYPICAL APPLICATIONS
INPUT INDUCTOR (L1) SELECTION
The central component in the regulator is the input boost
inductor. The value of this inductor controls various
critical operational aspects of the regulator. If the value is
too low, the input current distortion will be high and will
result in low power factor and increased noise at the
input. This will require more input filtering. In addition,
when the value of the inductor is low the inductor dries
out (runs out of current) at low currents. Thus the power
factor will decrease at lower power levels and/or higher
line voltages. If the inductor value is too high, then for a
given operating current the required size of the inductor
core will be large and/or the required number of turns
will be high. So a balance must be reached between
distortion and core size.
One more condition where the inductor can dry out is
analyzed below where it is shown to be maximum duty
cycle dependent.
For the boost converter at steady state:
V
V
D
OUT
IN
ON
=
-
1
(1)
Where D
ON
is the duty cycle [T
ON
/(T
ON
+ T
OFF
)]. The
input boost inductor will dry out when the following
condition is satisfied:
V t V
D
IN
OUT
ON
( )
(
)
<
´ -
1
(2)
or
V
D
V
INDRY
ON
OUT
= -
´
[
(max)]
1
(3)
V
INDRY
: voltage where the inductor dries out.
V
OUT
: output DC voltage.
Effectively, the above relationship shows that the resetting
volt-seconds are more than setting volt-seconds. In energy
transfer terms this means that less energy is stored in the
inductor during the ON time than it is asked to deliver
during the OFF time. The net result is that the inductor
dries out.
ML4812
8
The recommended maximum duty cycle is 95% at
100KHz to allow time for the input inductor to dump its
energy to the output capacitors. For example, if: V
OUT
=
380V and D
ON
(max) = 0.95, then substituting in (3)
yields V
INDRY
= 20V. The effect of drying out is an
increase in distortion at low voltages.
For a given output power, the instantaneous value of the
input current is a function of the input sinusoidal voltage
waveform, i.e. as the input voltage sweeps from zero volts
to a maximum value equal to its peak so does the current.
The load of the power factor regulator is usually a
switching power supply which is essentially a constant
power load. As a result, an increase in the input voltage
will be offset by a decrease in the input current.
By combining the ideas set forth above, some ground
rules can be obtained for the selection and design of the
input inductor:
Step 1: Find minimum operating current.
I
P
V
IN
PEAK
IN
IN
(min)
.
(min)
(max)
=
´
1414
(4)
V
IN
(max) = 260V
P
IN
(min) = 50W
then:
I
IN
(min)
PEAK
= 0.272A
Step 2: Choose a minimum current at which point the
inductor current will be on the verge of drying
out. For this example 40% of the peak current
found in step 1 was chosen.
then:
I
LDRY
= 100mA
Step 3: The value of the inductance can now be found
using previously calculated data.
L
V
D
I
f
V
mA
KHz
mH
INDRY
ON
LDRY
OSC
1
20
0 95
100
100
2
=
´
´
=
´
´
=
(max)
.
(5)
The inductor can be allowed to decrease in value when
the current sweeps from minimum to maximum value.
This allows the use of smaller core sizes. The only
requirement is that the ramp compensation must be
adequate for the lower inductance value of the core so
that there is adequate compensation at high current.
Step 4: The presence of the ramp compensation will
change the dry out point, but the value found
above can be considered a good starting point.
Based on the amount of power factor correction
the above value of L1 can be optimized after a
few iterations.
Gapped Ferrites, Molypermalloy, and Powdered Iron
cores are typical choices for core material. The core
material selected should have a high saturation point and
acceptable losses at the operating frequency.
One ferrite core that is suitable at around 200W is the
#4119PL00-3C8 made by Philips Components
(Ferroxcube). This ungapped core will require a total gap
of 0.180" for this application.
OSCILLATOR COMPONENT SELECTION
The oscillator timing components can be calculated by
using the following expression:
f
R
C
OSC