Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FUNCTIONAL BLOCK DIAGRAM
FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
OEBA
CLKBA
LEBA
OEAB
CLKAB
LEAB
B
1
C
C
A
1
D
D
2548 drw 01
D
C
D
C
TO 17 OTHER CHANNELS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
©
1996 Integrated Device Technology, Inc.
5.9
DSC-2548/7
1
IDT54/74FCT16500AT/CT/ET
IDT54/74FCT162500AT/CT/ET
bit registered transceivers are built using advanced dual metal
CMOS technology. These high-speed, low-power 18-bit reg-
istered bus transceivers combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched and clocked
modes. Data flow in each direction is controlled by output-
enable (OEAB and
OEBA
), latch enable (LEAB and LEBA)
and clock (
CLKAB
and
CLKBA
) inputs. For A-to-B data flow,
the device operates in transparent mode when LEAB is HIGH.
When LEAB is LOW, the A data is latched if
CLKAB
is held at
a HIGH or LOW logic level. If LEAB is LOW, the A bus data is
stored in the latch/flip-flop on the HIGH-to-LOW transition of
CLKAB
. OEAB performs the output enable function on the B
port. Data flow from B port to A port is similar but uses
OEBA
,
LEBA and
CLKBA
. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
The FCT16500AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
to allow "live insertion" of boards when used as backplane
drivers.
The FCT162500AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162500AT/CT/ET are plug-in replacements for the
FCT16500AT/CT/ET and ABT16500 for on-board bus inter-
face applications.
DESCRIPTION:
The FCT16500AT/CT/ET and FCT162500AT/CT/ET 18-
FEATURES:
• Common features:
–
0.5 MICRON CMOS Technology
–
High-speed, low-power CMOS replacement for
ABT functions
–
Typical t
SK
(o) (Output Skew) < 250ps
–
Low input and output leakage
≤
1
µ
A (max.)
–
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
–
Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
–
Extended commercial range of -40
°
C to +85
°
C
–
V
CC
= 5V
±
10%
• Features for FCT16500AT/CT/ET:
–
High drive outputs (-32mA I
OH
, 64mA I
OL
)
–
Power off disable outputs permit “live insertion”
–
Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25
°
C
• Features for FCT162500AT/CT/ET:
–
Balanced Output Drivers:
±
24mA (commercial),
±
16mA (military)
–
Reduced system switching noise
–
Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25
°
C
5.9
2
IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
GND
B
2
B
3
GND
B
4
B
5
V
CC
B
6
B
7
B
1
B
8
B
9
B
10
B
11
GND
B
12
B
13
V
CC
B
14
GND
CLKAB
B
16
B
15
B
17
GND
B
18
GND
CLKBA
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
GND
A
6
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
18
A
14
A
13
A
16
GND
A
17
LEBA
A
15
OEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
32
25
26
27
28
2548 drw 03
CERPACK
TOP VIEW
E56-1
GND
B
2
B
3
GND
B
4
B
5
V
CC
B
6
B
7
B
1
B
8
B
9
B
10
B
11
GND
B
12
B
13
V
CC
B
14
GND
CLKAB
B
16
B
15
B
17
GND
B
18
GND
CLKBA
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
GND
A
6
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
18
A
14
A
13
A
16
GND
A
17
LEBA
A
15
OEBA
2548 drw 02
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
SSOP/
TSSOP/TVSOP
TOP VIEW
SO56-1
SO56-2
SO56-3
29
30
31
32
25
26
27
28
IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5.9
3
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input (Active LOW)
CLKBA
B-to-A Clock Input (Active LOW)
Ax
A-to-B Data Inputs or B-to-A 3-State Outputs
Bx
B-to-A Data Inputs or A-to-B 3-State Outputs
2548 tbl 01
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
2548 tbl 02
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA
,
LEBA, and
CLKBA
.
2. Output level before the indicated steady-state input conditions were
established.
3. Output level before the indicated steady-state input conditions were
established, provided that
CLKAB
was LOW before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↓ =
HIGH-to-LOW Transition
2548 lnk 04
CAPACITANCE
(T
A
= +25
°
C, f = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
(1,4)
Inputs
Outputs
OEAB
LEAB
CLKAB
CLKAB
Ax
Bx
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
↓
L
L
H
L
↓
H
H
H
L
H
X
B
(2)
H
L
L
X
B
(3)
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input
Capacitance
V
IN
= 0V
3.5
6.0
pF
C
I/O
I/O
Capacitance
V
OUT
= 0V
3.5
8.0
pF
Symbol
Description
Max.
Unit
V
TERM(2)
Terminal Voltage with Respect to
GND
–0.5 to +7.0
V
V
TERM(3)
Terminal Voltage with Respect to
GND
–0.5 to
V
CC
+0.5
V
T
STG
Storage Temperature
–65 to +150
°
C
I
OUT
DC Output Current
–60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. All device terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
2548 lnk 03
5.9
4
IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= –40
°
C to +85
°
C, V
CC
= 5.0V
±
10%; Military: T
A
= –55
°
C to +125
°
C, V
CC
= 5.0V
±
10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
—
—
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
I
I H
Input HIGH Current (Input pins)
(5)
V
CC
= Max.
V
I
= V
CC
—
—
±
1
µ
A
Input HIGH Current (I/O pins)
(5)
—
—
±
1
I
I L
Input LOW Current (Input pins)
(5)
V
I
= GND
—
—
±
1
Input LOW Current (I/O pins)
(5)
—
—
±
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
—
—
±
1
µ
A
I
OZL
(3-State Output pins)
(5)
V
O
= 0.5V
—
—
±
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= –18mA
—
–
0.7
–
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
–80
–
140
–
225
mA
V
H
Input Hysteresis
—
—
100
—
mV
I
CCL
I
CCH
I
CCZ
Quiescent Power Supply Current
V
CC
= Max., V
IN
= GND or V
CC
—
5
500
µ
A
2548 lnk 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16500T
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
O
Output Drive Current
V
CC
= Max., V
O
= 2.5V
(3)
–50
—
–
180
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= –3mA
2.5
3.5
—
V
V
IN
= V
IH
or V
IL
I
OH
= –12mA MIL.
I
OH
= –15mA COM'L.
2.4
3.5
—
V
I
OH
= –24mA MIL.
I
OH
= –32mA COM'L.
(4)
2.0
3.0
—
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 48mA MIL.
I
OL
= 64mA COM'L.
—
0.2
0.55
V
I
OFF
Input/Output Power Off Leakage
(5)
V
CC
= 0V, V
IN
or V
O
≤
4.5V
—
—
±
1
µ
A
2548 lnk 06
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25
°
C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is
±
5
µ
A at T
A
= –55
°
C.
OUTPUT DRIVE CHARACTERISTICS FOR FCT162500T
2548 lnk 07
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
or
V
IL,
V
OUT
= 1.5V
(3)
60
115
200
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
or V
IL,
V
OUT
= 1.5V
(3)
–60
–115
–200
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –16mA MIL.
I
OH
= –24mA COM'L.
2.4
3.3
—
V
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OL
= 16mA MIL.
I
OL
= 24mA COM'L.
—
0.3
0.55
V
IDT54/74FCT16500AT/CT/ET, 162500AT/CT/ET
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5.9
5
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
∆
I
CC
Quiescent Power Supply
V
CC
= Max.
—
0.5
1.5
mA
Current TTL Inputs HIGH
V
IN
= 3.4V
(3)
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max., Outputs Open
V
IN
= V
CC
—
75
120
µ
A/
OEAB =
OEBA
= V
CC
or GND V
IN
= GND
MHz
One Input Toggling
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max., Outputs Open
V
IN
= V
CC
—
0.8
1.7
mA
f
CP
= 10MHz (
CLKAB
)
V
IN
= GND
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND
V
IN
= 3.4V
—
1.3
3.2
One Bit Toggling
V
IN
= GND
f
i
=
5MHz
50% Duty Cycle
V
CC
= Max., Outputs Open
V
IN
= V
CC
—
3.8
6.5
(5)
f
CP
= 10MHz (
CLKAB
)
V
IN
= GND
50% Duty Cycle
OEAB =
OEBA
= V
CC
LEAB = GND
V
IN
= 3.4V
—
8.5
20.8
(5)
Eighteen Bits Toggling
V
IN
= GND
f
i
=
2.5MHz
50% Duty Cycle
2548 tbl 08
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25
°
C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
∆
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T