Microsoft Word - VES1848rev12jul99

comatlas S.A., 30 rue du Chêne Germain, BP 814, 35518 CESSON SEVIGNE Cedex, France

Phone : + 33 2 99 27 55 55 – Fax : +33 2 99 27 55 27, Internet : www.comatlas.fr / VES 1848 rev 1.2 / July 99

VES 1848

SINGLE CHIP

DAVIC / DVB-RC

CABLE MODEM

FEATURES

•

Fully compliant ETS300800 and DAVIC 1.2

•

Out-Off Band demodulation scheme :

On chip 7-bit ADC.

DQPSK demodulator.

Roll-off factor = 0.3 .

Direct IF sampling.

Variable bit rate from 1 to 12 Mbit/s (SAW

@ 8MHz BW).

Automatic Gain Control PWM output.

Descrambler.

Frame synchronization.

Deinterleaver.

RS decoder (55,53) .

•

In Band scheme :

Parallel or serial MPEG2 Transport Stream

inputs.

MAC PID filtering.

DAVIC ATM cells transmission supported.

•

Up-Stream synchronization.

•

Up-Stream modulation scheme :

Burst QPSK/16QAM modulator.

Roll-off factor = 0.25/0.3 .

Programmable preamble value.

Programmable burst length.

Direct IF synthesys from 5 to 46 MHz.

I and Q base band outputs provided.

Variable bit rate from 256kbit/s to 16Mbit/s.

Programmable RS encoder.

Scrambler.

On chip 10 bit DACs.

•

External MAC functionality.

•

Package 208 MQFP.

•

CMOS technology (0.35

m, 3.3V).

APPLICATIONS

•

Cable modem.

•

DVB interactive set-top box.

•

DAVIC ATM cable physical layer.

DESCRIPTION

Based on the DVB-RC cable and DAVIC

specifications, the VES 1848 allows interactive

communication through HFC network between set-

top boxes and headends.

For Down Stream (DS) channel the circuit

implements a differential QPSK demodulator (Out Of

Band application) and accepts MPEG2 Transport

Stream inputs from a DS QAM demodulator (In Band

application). This channel allows to synchronize the

Up Stream (US) channel and to provide data to the

MAC layer which remains external.

The US channel is highly programmable and built

around a digital burst QPSK or 16QAM modulator

with direct IF synthesys or I and Q base band

outputs. The modulator is fully DVB and MCNS

compliant thanks to its burst profile programmation

(burst length, preamble, RS encoder, scrambler, bit

rate …).

The VES 1848 is packaged in a 208 MQFP, and

operates over the commercial temperature 0-70°C.

comatlas reserves the right to make any change at any time without notice.

VES 1848 rev 1.2 / July 99 / p 2

SUMMARY

CAUTION

This document is preliminary and is subject to change. Contact a

comatlas representative to determine if this is the current information

on this device.

The information contained in this document has been carefully checked and is believed to be reliable. However,

comatlas makes no guarantee or warranty concerning the accuracy of said information and shall not be

responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, it. comatlas

does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark,

This document does not in any way extend comatlas warranty on any product beyond that set forth in its

standard terms and conditions of sale. comatlas reserves the right to make changes in the products or

specifications, or both, presented in this publication at any time and without notice.

LIFE SUPPORT APPLICATIONS : comatlas products are not intended for use as critical components in life

support appliances, devices, or systems in which the failure of a comatlas product to perform could be expected

to result in personal injury.

comatlas reserves the right to make any change at any time without notice.

VES 1848 rev 1.2 / July 99 / p 3

1 GENERAL

DESCRIPTION

FIGURE

1 : FUNCTIONAL BLOCK DIAGRAM

interface

application layers

interface

MAC

Up Stream

synchronisation

external

synchro

channel processing

Out Of Band

DQPSK

demodulator

ADC

fixed

QPSK / 16QAM

burst modulator

DAC

Up Stream

channel encoding

programmable

In Band

channel processing

symbol clock

MPEG2-TS

IF or I

1.1 ABREVIATIONS

AGC

Automatic Gain Control

Bandwidth

CRC

Cyclic Redundancy Checking (type of error correction code)

Down Stream (from the Headend to the set-top box)

Headend

HEC

Header Error Control (CRC of the ATM cell header)

In Band

Intermediate Frequency

NIU

Network Interface Unit (physical and MAC layers of the STB)

OOB

Out Of Band

PWM

Pulse Wave Modulation

SL-ESF

Signalling Link Extended SuperFrame (name of the OOB frame)

STB

Set-Top Box

Up Stream (from the set-top box to the headend)

Unique Word (=preamble)

1.2 NOTATION

References to programmation registers are done this way :

AD.7 = bit 7 (in decimal) of the register located at the address AD (in hexa).

AD.[7-5] = bits 7 down to 5 of the register located at the address AD.

1.3 FUNCTIONAL

DESCRIPTION

ADC

The VES 1848 implements a 7-bit analog to digital converter. It directly samples the OOB IF signal. The IF value

can be chosen by the system designer.

comatlas reserves the right to make any change at any time without notice.

VES 1848 rev 1.2 / July 99 / p 4

DQPSK

DEMODULATOR

Fully digital variable bitrate demodulator used for the OOB channel. It implements a digital down conversion to

base band, filtering and decimation, frequency and clock recoveries as well as equalization. It also provides an

AGC command to the OOB tuner.

OOB CHANNEL PROCESSING

After descrambling, deframing and deinterleaving, ATM cells are fed into the RS decoder and corrected. A filtering

on ATM headers and MAC headers is then done on valid cells to keep only those addressed to the STB. MAC cells

and application layers cells are stored in 2 different FIFOs. Up to 4 different VPI-VCI can be filtered for application

layers data.

Mbits and Rxbits

(1)

are also output after integrity checking.

For US synchronization, 3ms markers are generated.

IB CHANNEL PROCESSING

This block is fed with the outputs of a cable FEC decoder. It implements the filtering of the MAC data addressed to

the STB as well as valid time references and valid Rxbits filtering.

Mbits, Rxbits (after integrity checking) and MAC data are stored in a FIFO.

For US synchronization, 3ms markers are generated.

No PID filtering is done for application layers data.

This block implements the filtering of ATM cells transported in MPEG2-TS packet as defined by DAVIC. These data

are stored in the application layers FIFO and up to 4 different VPI-VCI can be filtered.

INTERFACES

MAC messages and application layers data are stored in different FIFOs. They can then be read/write with the

same or 2 different micro processor interfaces.

The VES 1848 registers are programmed with the MAC interface.

SYNCHRONIZATION

This block decides when to send an US burst.

When the VES 1848 is used in a DVB/DAVIC device, this block also does the propagation delay compensation and

the US slot numbering. It uses information from the DS channel (Mbits, 3ms markers) and some provided by the

MAC layer (time compensation, slot number where to send a burst).

When the US path is used in a MCNS device, the burst start information is provided by the toggle of the external

synchro pin.

CHANNEL

ENCODING

It is DVB/DAVIC and MCNS compliant thanks to its burst profile programmation (6 different profiles can be stored

in the VES 1848).

Data read in FIFOs are RS encoded, randomized and differential encoded before the addition of a programmable

preamble.

BURST

MODULATOR

Data can be output either in base band after predistorsion and nyquist filtering or directly on a programmable IF. In

that case a programmable sinewave can also be generated if required.

DAC

Two 10-bit Digital to Analog Converters are built in the VES 1848. The modulated data are provided on both analog

and digital outputs.

(1)

refer to the DVB or DAVIC specification for the definition of Mbits and Rxbits.

comatlas reserves the right to make any change at any time without notice.

VES 1848 rev 1.2 / July 99 / p 5

TABLE 1: ABSOLUTE MAXIMUM RATINGS

Parameter

Min

Max

Unit

Ambient operating temperature : Ta

°C

DC supply voltage (VDD)

- 0.5

+ 4.1

DC Input voltage

- 0.5

VDD + 0.5

DC Input Current

± 20

Lead Temperature

+300

°C

Junction Temperature

+150

°C

Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to

absolute maximum ratings conditions for extended periods may affect device reliability.

TABLE 2 : RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Typ

Max

Unit

Notes

VDD

VD1, VD1IQ

Digital supply voltage

3.14

3.3

3.46

3.3V ±5%

VCC

5V supply

4.75

5.25

Operating temperature

°C

Ambient temperature

VIH

(1)

High-level input voltage

VCC + 0.3

TTL input

VIL

Low-level input voltage

-0.5

0.8

TTL input

VOH

(2)

High-level output voltage VDD -0.1

2.4

@ IOH = -0.8 mA

@ IOH = + 2mA

VOL

Low-level output voltage

0.1

0.4

@ IOL = 0.8 mA

@ IOL = + 2mA

IDD + ICC

Supply current

300

@US_clk = 116MHz

(3)

CIN

Input capacitance

COUT

Output capacitance

VD2

VD3, VD4

AVDDI, AVDDQ

VD0I, VD0Q

Analog supply voltage

3.14

3.3

3.46

3.3V ± 5%

DAC full scale output

current range

DAC termination resistor

ohms

(1)

All inputs are 5V tolerant.

(2)

IOH, IOL =

4mA only for pins DATAA, DATAM, INTA, INTM, VAGC, PWM2, FCONTI, SDAOUT, SDAIN,

SCLOUT, WRNA, RDN_ENAA, CSA, US_SACLK.

(3)

with the US modulator working in continuous mode and with direct IF synthesys.

comatlas reserves the right to make any change at any time without notice.

VES 1848 rev 1.2 / July 99 / p 6

TABLE 3 : ANALOG CHARACTERISTICS

Symbol

Parameter

Min

Typ

Max

Unit

Notes

VIP-VIM

ADC input signal range

-0.5

0.5

ADC Rin

ADC input Resistance

kohms

ADC Cin

ADC capacitance

(VIP or VIM)

ADC BW

OOB ADC input full

power bandwidth

MHZ

0.1dB bandwith

FS147

DAC full scale output

current

(on Iana and Qana)

VrefIQ=1.235V

IrefI and irefQ

connected to a

147

Ω

resistor,

US_clk = 60MHz

Voc

DAC output voltage

compliance

1.0

1.05

Vout

≤

1.0V

≤

75 ohms

SFRD

DAC spurious Free

Dynamic Range

-50

DBc

= 37.5 ohms

US_clk = 58 MHz

Input data

frequency

= 0.3 US_clk

comatlas reserves the right to make any change at any time without notice.

VES 1848 rev 1.2 / July 99 / p 7

FIGURE 2 : INPUT-OUTPUT BLOCK DIAGRAM

VIM

VIP

OOB_dig

scan_en

IDDQ

test

SCLin

SDAin

SDAout

SCLout

Tmode

switch

test

OOB analog

OOB_clk_in

OOB_clk_out

US_clk_in

US_clk_out

Doob

clk_OOB

OOB_saclk

vagc

PWM2

IBsymbclk

IBclk

Psync

power supplies

VDD

VSS

VCC

Iana

EXT_SYNC

Fconti

Iconti

Qconti

on_off

PctrPWM

Qana

US_saclk

I_IF

OOB

VES1848

dataM

intM

hmuxmodeM

hstbmodeM

csM

rdn_enaM

wrnM

aleM

dataA

intA

hmuxmodeA

hstbmodeA

csA

rdn_enaA

wrnA

aleA

addM

addA

MAC

interface

application layers

utopia

nb_micro

Fmicro

RESET

start_slot_US

ctrl

DS_3ms

control

interface

comatlas reserves the right to make any change at any time without notice.

VES 1848 rev 1.2 / July 99 / p 8

FIGURE 3 : PIN DIAGRAM

107

105

106

108

109

111

110

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

VES1848

VD1

CMI

CMCAP

VREFP

VIM

VIP

VS2

VD2

VD4

VREF

VD3

VS3

VREFM

RBIAS

VS1

CMO

VSS

VCC

VSS

Q[0]

Q[1]

Q[2]

Q[3]

VSS

VDD

Q[4]

Q[5]

Q[6]

Q[7]

VSS

VDD

Q[8]

Q[9]

US_SACLK

I_IF[0]

I_IF[1]

VSS

VDD

I_IF[2]

I_IF[3]

I_IF[4]

I_IF[5]

VSS

I_IF[6]

I_IF[7]

I_IF[8]

I_IF[9]

DS_3ms

start_slot_us

VDD

SDAin

addA[0]

csA

aleA

wrnA

dataA[1]

dataA[5]

dataA[6]

dataA[7]

dataA[8]

dataA[3]

dataA[0]

addA[4]

dataA[10]

dataA[12]

dataA[13]

dataA[14]

dataA[15]

hmuxmodeA

hstbmodeA

intM

wrnM

rdn_enaM

addM[0]

addM[1]

addM[2]

addM[3]

addM[4]

addM[5]

addM[6]

addM[7]

dataM[1]

dataM[0]

dataM[2]

dataM[3]

dataM[4]

dataM[5]

dataM[6]

dataM[7]

csM

aleM

hmuxmodeM

hstbmodeM

nb_micro

VDD

VSS

Fmicro

IBsymbclk

IBclk

PSYNC

IB[0]

IB[1]

IB[2]

IB[3]

IB[4]

IB[5]

IB[6]

IB[7]

SCAN_EN

Tmode

IDDQ

clk_oob

Doob

OOB_dig[6]

VDD

TEST

Qconti[0]

Qconti[1]

Qconti[2]

Iconti[0]

Iconti[1]

Iconti[2]

EXT_SYNC

Fconti

irefI

compI

Iana

vrefIQ

avssI

avddI

vs0I

vd0I

vs1IQ

Qana

vd0Q

vs0Q

irefQ

compQ

vd1IQ

PctrPWM

OnOff

US_clk_out

US_clk_in

SDAout

VSS

SCLin

SCLout

VDD

VSS

intA

rdn_enaA

VSS

VCC

addA[1]

addA[3]

addA[2]

dataA[2]

dataA[4]

dataA[9]

dataA[11]

OOB_clk_in

OOB_clk_out

OOB_dig[5]

OOB_dig[4]

OOB_dig[3]

OOB_dig[2]

OOB_dig[1]

OOB_dig[0]

OOB_SACLK

VSS

VCC

VAGC

PWM2

VSS

RESET

VSS

VDD

utopia

VCC

VSS

VDD

VSS

VDD

avssQ

avddQ

CTRL1

CTRL2

CTRL3

VS4

CTRL0

comatlas reserves the right to make any change at any time without notice.

VES 1848 rev 1.2 / July 99 / p 9

TABLE 4 : PIN DESCRIPTION

Pin

Pin Name

Direction

dataA[15]

I /O

hmuxmodeA

hstbmodeA

VCC

VSS

intM

wrnM

rdn_enaM

addM[0]

addM[1]

addM[2]

addM[3]

addM[4]

VDD

VSS

addM[5]

addM[6]

addM[7]

dataM[0]

I/O

dataM[1]

I/O

dataM[2]

I/O

dataM[3]

I/O

dataM[4]

I/O

VCC

VSS

dataM[5]

I/O

dataM[6]

I/O

dataM[7]

I/O

csM

aleM

hmuxmodeM

hstbmodeM

utopia

VDD

VSS

nb_micro

Fmicro

IBsymbclk

IBclk

PSYNC

IB[0]

IB[1]

Pins 56 to 72 as well as all input

pins not used must be grounded.

Pin

Pin Name

Direction

VCC

VSS

IB[2]

IB[3]

IB[4]

IB[5]

IB[6]

IB[7]

SCAN_EN

Tmode

IDDQ

Doob

clk_oob

Not used

VDD

VSS

RESET

TEST

VSS

OOB_clk_in

OOB_clk_out

VDD

PWM2

VAGC

VCC

VSS

Pin

Pin Name

Direction

OOB_SACLK

OOB_dig[0]

OOB_dig[1]

OOB_dig[2]

OOB_dig[3]

OOB_dig[4]