Semiconductor Group 1 6.97
•
16 777 216 words by 4-bit organization
•
0 to 70 °C operating temperature
•
Hyper Page Mode - EDO - operation
•
Performance:
•
Single + 3.3 V (
±
0.3V) power supply
•
Low power dissipation:
max. 450 active mW ( HYB 3164405AJ/AT(L)-40)
max. 360 active mW ( HYB 3164405AJ/AT(L)-50)
max. 324 active mW ( HYB 3164405AJ/AT(L)-60)
max. 612 active mW ( HYB 3165405AJ/AT(L)-40)
max. 405 active mW ( HYB 3165405AJ/AT(L)-50)
max. 432 active mW ( HYB 3165405AJ/AT(L)-60)
7.2 mW standby (LVTTL)
3.24 mW standby (LVMOS)
720
µ
A standby for L-version
•
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh
•
Self refresh (L-version only)
•
8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164405AJ/AT)
4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165405AJ/AT)
•
256 msec refresh period for L-versions
•
Plastic Package:
P-SOJ-32-1 400 mil HYB 3164(5)400AJ
P-TSOPII-32-1 400 mil HYB 3164(5)400AT(L)
-40
-50
-60
t
RAC
RAS access time
40
50
60
ns
t
CAC
CAS access time
10
13
15
ns
t
AA
Access time from address
20
25
30
ns
t
RC
Read/write cycle time
69
84
104
ns
t
HPC
Hyper page mode (EDO)
cycle time
16
20
25
ns
HYB 3164405AJ/AT(L) -40/-50/-60
HYB 3165405AJ/AT(L) -40/-50/-60
16M x 4-Bit Dynamic RAM
(4k & 8k Refresh, EDO-Version)
Advanced Information
Semiconductor Group
2
HYB3164(5)405AJ/AT(L)-40/-50/-60
16M x 4-DRAM
This HYB3164(5)405A is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is
fabricated on an advanced second generation 64Mbit 0,35
µ
m-CMOS silicon gate process
technology. The circuit and process design allow this device to achieve high performance and low
power dissipation. The HYB3164(5)405A operates with a single 3.3 +/-0.3V power supply and
interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB
3164(5)405A to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package. These
packages provide high system bit densities and are compatible with commonly used automatic
testing and insertion equipment.The HYB3164(5)405ATL parts have a very low power „sleep mode“
supported by Self Refresh.
Ordering Information
Type
Ordering
Code
Package
Descriptions
8k-refresh versions:
HYB 3164405AJ-40
P-SOJ-32-1 400 mil
DRAM (access time 40 ns)
HYB 3164405AJ-50
P-SOJ-32-1 400 mil
DRAM (access time 50 ns)
HYB 3164405AJ-60
P-SOJ-32-1 400 mil
DRAM (access time 60 ns)
HYB 3164405AT-40
P-TSOPII-32-1 400 mil
DRAM (access time 40 ns)
HYB 3164405AT-50
P-TSOPII-32-1 400 mil
DRAM (access time 50 ns)
HYB 3164405AT-60
P-TSOPII-32-1 400 mil
DRAM (access time 60 ns)
HYB 3164405ATL-50
P-TSOPII-32-1 400 mil
DRAM (access time 50 ns)
HYB 3164405ATL-60
P-TSOPII-32-1 400 mil
DRAM (access time 60 ns)
4k-refresh versions:
HYB 3165405AJ-40
P-SOJ-32-1 400 mil
DRAM (access time 40 ns)
HYB 3165405AJ-50
P-SOJ-32-1 400 mil
DRAM (access time 50 ns)
HYB 3165405AJ-60
P-SOJ-32-1 400 mil
DRAM (access time 60 ns)
HYB 3165405AT-40
P-TSOPII-32-1 400 mil
DRAM (access time 40 ns)
HYB 3165405AT-50
P-TSOPII-32-1 400 mil
DRAM (access time 50 ns)
HYB 3165405AT-60
P-TSOPII-32-1 400 mil
DRAM (access time 60 ns)
HYB 3165405ATL-50
P-TSOPII-32-1 400 mil
DRAM (access time 50 ns)
HYB 3165405ATL-60
P-TSOPII-32-1 400 mil
DRAM (access time 60 ns)
Semiconductor Group
3
HYB3164(5)405AJ/AT(L)-40/-50/-60
16M x 4-DRAM
Pin Configuration
Pin Names
A0-A12
Address Inputs for 8k-refresh version HYB 3164405AJ/AT(L)
A0-A11
Address Inputs for 4k-refresh version HYB 3165405AJ/AT(L)
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O4
Data Input/Output
CAS
Column Address Strobe
WE
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
P-SOJ-32-1 (400 mil)
* Pin 24 is A12 for HYB 3164405AJ/AT(L) and N.C. for HYB 3165405AJ/AT(L)
P-TSOPII-32-1 (400 mil)
1
2
3
4
5
6
9
10
11
12
13
14
23
24
25
26
27
28
VSS
I/O4
I/O3
N.C.
N.C.
CAS
VCC
I/O1
I/O2
N.C.
A0
A1
A2
A3
VCC
18
19
20
O
OE
WE
N.C.
7
22
21
8
RAS
15
16
N.C.
N.C.
.
A4
A5
32
31
30
29
N.C.
A12 / N.C. *
A11
A10
A9
A8
A7
A6
VSS
17
Semiconductor Group
4
HYB3164(5)405AJ/AT(L)-40/-50/-60
16M x 4-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WE
OE
ROW
ADDR
COL
ADDR
I/O1-
I/O4
Standby
H
H - X
X
X
X
X
High Impedance
Read
L
L
H
L
ROW
COL
Data Out
Early-Write
L
L
L
X
ROW
COL
Data In
Delayed-Write
L
L
H - L
H
ROW
COL
Data In
Read-Modify-Write
L
L
H - L
L - H
ROW
COL
Data Out, Data In
Hyper Page Mode Read
1st Cycle
L
H - L
H
L
ROW
COL
Data Out
2nd Cycle
L
H - L
H
L
n/a
COL
Data Out
Hyper Page Mode Write 1st Cycle
L
H - L
L
X
ROW
COL
Data In
2nd Cycle
L
H - L
L
X
n/a
COL
Data In
Hyper Page Mode RMW 1st Cycle
L
H - L
H - L
L - H
ROW
COL
Data Out, Data In
2st Cycle
L
H - L
H - L
L - H
n/a
COL
Data Out, Data In
RAS only refresh
L
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS refresh
H - L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H - L
L
L
X
X
n/a
High Impedance
Hidden Refresh
READ
L-H-L
L
H
L
ROW
COL
Data Out
WRITE
L-H-L
L
L
X
ROW
COL
Data In
Self Refresh
(L-version only)
H - L
L
H
X
X
X
High Impedance
Semiconductor Group
5
HYB3164(5)405AJ/AT(L)-40/-50/-60
16M x 4-DRAM
Block Diagram for HYB 3165405AJ/AT(L)
No. 2 Clock
Generator
Column
Address
Buffer(12)
Refresh
Controller
Refresh
Counter (12)
Address
Buffers(12)
Row
No. 1 Clock
Generator
&
Data in
Buffer
Data out
Buffer
Column
Decoder
Sense Amplifier
I/O Gating
Memory Array
4096 x 4096 x 4
Row
Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
WE
CAS
4096
4096
x4
.
RAS
12
12
4
I/O1
I
/O2
OE
12
12
A10
A11
4
4
12
I/O4
Semiconductor Group
6
HYB3164(5)405AJ/AT(L)-40/-50/-60
16M x 4-DRAM
Block Diagram for HYB 3164405AJ/AT(L)
No. 2 Clock
Generator
Column
Address
Buffer(11)
Refresh
Controller
Refresh
Counter (13)
Address
Buffers(13)
Row
No. 1 Clock
Generator
&
Data in
Buffer
Data out
Buffer
Column
Decoder
Sense Amplifier
I/O Gating
Memory Array
8192 x 2048 x 4
Row
Decoder
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
WE
CAS
8192
2048
x4
.
RAS
11
13
4
I/O1
I
/O2
OE
13
13
A10
A11
4
4
11
I/O4
A12
Semiconductor Group
7
HYB3164(5)405AJ/AT(L)-40/-50/-60
16M x 4-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V
Parameter
Symbol
Limit Values
Unit Note
min.
max.
Input high voltage
V
IH
2.0
Vcc+0.3
V
1)
Input low voltage
V
IL
– 0.3
0.8
V
1)
Output high voltage (LVTTL)
Output „H“ level voltage (Iout = -2mA)
V
OH
2.4
–
V
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
V
OL
–
0.4
V
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
V
OH
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
V
OL
-
0.2
V
Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
I
I(L)
– 2
2
µ
A
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
I
O(L)
– 2
2
µ
A
Semiconductor Group
8
HYB3164(5)405AJ/AT(L)-40/-50/-60
16M x 4-DRAM
DC-Characteristics (cont’d)
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V
Parameter
Symbol refresh
version Unit Note
4k row
8k row
Operating Current
-40 ns version
-50 ns version
- -60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
I
CC1
170
140
115
125
100
85
mA
mA
mA
2) 3) 4)
Standby Current (
RAS
=
CAS
=
Vih
)
I
CC2
2
2
mA
–
RAS Only Refresh Current:
- - 40 ns version
-50 ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
I
CC3
170
140
115
125
100
85
mA
mA
mA
2) 4)
Hyper Page Mode (EDO) Current:
-40 ns version
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling: tHPC=tHPC min.)
I
CC4
140
105
85
140
105
85
mA
mA
2) 3) 4)
Standby Current (
RAS
=
CAS
=
Vcc-0.2V
)
I
CC5
900
900
µ
A
–
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
I
CC5
200
200
µ
A
–
CAS Before RAS Refresh Current
- 40 ns version
-50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
I
CC6
170
140
115
170
140
115
mA
mA
2) 4)
Self Refresh Current (L-version only)
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
I
CC7
400
400
µ
A
Capacitance
T
A
= 0 to 70 °C,
V
CC
= 3.3 V
±
0.3 V,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A11,A12)
C
I1
–
5
pF
Input capacitance (RAS, CAS, WE, OE)
C
I2
–
7
pF
I/O capacitance (I/O1-I/O4)
C
IO
–
7
pF
Semiconductor Group
9
HYB3164(5)405AJ/AT(L)-40/-50/-60
16M x 4-DRAM
AC Characteristics
5)6)
AC64-2E
T
A
= 0 to 70 °C,
V
CC
= 3.3 V
±
0.3V ,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
- 40
- 50
- 60
min.
max.
min.
max.
min.
max.
Common Parameters
Random read or write cycle time
t
RC
69
–
84
–
104
–
ns
RAS pulse width
t
RAS
40
100k
50
100k
60
100k
ns
CAS pulse width
t
CAS
6
100k
8
100k
10
100k
ns
RAS precharge time
t
RP
25
–
30
–
40
–
ns
CAS precharge time
t
CP
6
–
8
–
10
–
ns
Row address setup time
t
ASR
0
–
0
–
0
–
ns
Row address hold time
t
RAH
5
–
7
–
10
–
ns
Column address setup time
t
ASC
0
–
0
–
0
–
ns
Column address hold time
t
CAH
5
–
7
–
10
–
ns
RAS to CAS delay time
t
RCD
9
30
11
37
14
45
ns
RAS to column address delay time
t
RAD
7
20
9
25
12
30
ns
RAS hold time
t
RSH
6
–
8
10
–
ns
CAS hold time
t
CSH
32
–
40
48
–
ns
CAS to RAS precharge time
t
CRP
5
–
5
–
5
–
ns
Transition time (rise and fall)
t
T
1
50
1
50
1
50
ns
7
Refresh period for 8k-refresh-version
t
REF
–
128
–
128
–
128
ms
Refresh period for 4k-refresh version
t
REF
–
64
–
64
–
64
ms
Refresh period for L-versions
t
REF
–
256
–
256
–
256
ms
Read Cycle
Access time from RAS
t
RAC
–
40
–
50
–
60
ns
8, 9
Access time from CAS
t
CAC
–
10
–
13
–
15
ns
8, 9
Access time from column address
t
AA
–
20
–
25
–
30
ns
8,10
OE access time
t
OEA
–
10
–
13
–
15
ns
Column address to RAS lead time
t
RAL
20
–
25
–
30
–
ns
Read command setup time
t
RCS
0
–
0
–
0
–
ns
Read command hold time
t
RCH
0
–
0
–
0
–
ns
11
Semiconductor Group
10
HYB3164(5)405AJ/AT(L)-40/-50/-60
16M x 4-DRAM
Read command hold time
referenced to RAS
t
RRH
0
–
0
–
0
–
ns
11
CAS to output in low-Z
t
CLZ
0
–
0
–
0
–
ns
8
Output buffer turn-off delay
t
OFF
0
10
0
13
0
15
ns
12
Output buffer turn-off delay from OE
t
OEZ
0
10
0
13
0
15
ns
12
Data to CAS low delay
t
DZC
0
–
0
–
0
–
ns
13
Data to OE low delay
t
DZO
0
–
0
–
0
–
ns
13
CAS high to data delay
t
CDD
10
–
13
–
15
–
ns
14
OE high to data delay
t
ODD
10
–
13
–
15 –
ns
14
Write Cycle
Write command hold time
t
WCH
5
–
7
–
10
–
ns
Write command pulse width
t
WP
5
–
7
–
10
–
ns
Write command setup time
t
WCS
0
–
0
–
0
–
ns
15
Write command to RAS lead time
t
RWL
6
–
8
–