NS32FX161/NS32FX164/NS32FV16 Advanced Imaging/Communication Signal Processors

TL EE11267

NS32FX161-15NS32FX161-20NS32FX164-20NS32FX164-25NS32FV16-20NS32FV16-25

Advanced

ImagingCommunication

Signal

Processors

February 1992

NS32FX161-15 NS32FX161-20 NS32FX164-20

NS32FX164-25 NS32FV16-20 NS32FV16-25

Advanced Imaging Communication Signal Processors

General Description

The NS32FX164 the NS32FV16 and the NS32FX161 are

high-performance 32-bit members of the Series 32000

family of National’s Embedded System Processors

specifically optimized for CCITT Group 2 and Group 3 Fac-

simile Applications Data Modems Voice Mail Systems La-

ser Printers or any combination of the above

Unless

specified

otherwise

any

reference

the

NS32FX164 in this document applies to the NS32FV16 and

the NS32FX161 as well

The NS32FX164 can perform all the computations and con-

trol functions required for a stand-alone Fax system a PC

add-in Fax Voice Data Modem card or a Laser Fax sys-

tem

It also meets the performance requirements to implement

14400 9600 and 7200 bps modems complying with CCITT

V 17 V 29 and V 27 standards The NS32FV16 supports

V 29 and V 27 standards as well as voice The NS32FX161

supports V 29 and V 27 standards

The NS32FX164 provides a 16 Mbyte Linear external ad-

dress space and a 16-bit external data bus

The CPU core which is the same as that of the NS32CG16

incorporates a 32-bit ALU and instruction pipeline and an

8-byte prefetch queue

Also integrated on-chip with the CPU are a DSP Module

(DSPM) and a 4K-byte RAM Array (2K in the NS32FV16 and

NS32FX161) The DSPM is a complete processing unit ca-

pable of autonomous operation parallel to the CPU core

operation The DSPM executes programs stored in an inter-

nal on-chip Random Access Memory (RAM) and manipu-

lates data stored either in the internal RAM or in an external

off-chip memory To maximize utilization of hardware re-

sources the DSPM contains a pipelined DSP-oriented data-

path and a control logic that implements a set of DSP vec-

tor commands

The NS32FX164 capabilities can be expanded by using an

external floating point unit (FPU) which directly interfaces to

the NS32FX164 using the slave protocol The CPU-FPU

cluster features high speed execution of the floating-point

instructions

The NS32FX164 highly-efficient architecture combined with

the NS32CG16 graphics instructions and the high-perform-

ance vector operation capability makes the device the ideal

choice for Postscript

and Fax applications

Features

Software compatible with the Series 32000 EP

processors

Designed around the CPU core of the NS32CG16

Pin compatible with the NS32FX16

32-bit architecture and implementation

On-chip DSP Module for high-speed DSP operations

Special support for graphics applications

18 graphics instructions

Binary compression expansion capability for font

storage using RLL encoding

Pattern magnification

Interface to an external BITBLT processing units for

fast color BITBLT operations

4K-byte on-chip RAM array (2K in NS32FV16 and

NS32FX161)

On-chip clock generator

Floating-point support via the NS32081 or NS32181

Optimal interface to large memory arrays via the

NS32CG821 and the DP84xx family of DRAM

controllers

Power save mode

High-speed CMOS technology

68-pin PLCC package

Block Diagram

TL EE 11267 – 1

FIGURE 1-1 CPU Block Diagram

Series 32000

is a registered trademark of National Semiconductor Corporation

and Embedded System Processors

are trademarks of National Semiconductor Corporation

Postscript

is a trademark of Adobe Systems Inc

C1995 National Semiconductor Corporation

RRD-B30M115 Printed in U S A

Table of Contents

1 0 PRODUCT INTRODUCTION

1 1 NS32FX164 Special Features

2 0 ARCHITECTURAL DESCRIPTION

2 1 Register Set

2 1 1 General Purpose Registers

2 1 2 Address Registers

2 1 3 Processor Status Register

2 1 4 Configuration Register

2 1 5 DSP Module Registers

2 2 Memory Organization

2 2 1 Address Mapping

2 3 Modular Software Support

2 4 Instruction Set

2 4 1 General Instruction Format

2 4 2 Addressing Modes

2 4 3 Instruction Set Summary

2 5 Graphics Support

2 5 1 Frame Buffer Addressing

2 5 2 BITBLT Fundamentals

2 5 2 1 Frame Buffer Architecture

2 5 2 2 Bit Alignment

2 5 2 3 Block Boundaries and Destination

Masks

2 5 2 4 BITBLT Directions

2 5 2 5 BITBLT Variations

2 5 3 Graphics Support Instructions

2 5 3 1 BITBLT (BIT-aligned BLock Transfer) 23

2 5 3 2 Pattern Fill

2 5 3 3 Data Compression Expansion and

Magnify

2 5 3 3 1 Magnifying Compressed

Data

3 0 FUNCTIONAL DESCRIPTION

3 1 Instruction Execution

3 1 1 Operating States

3 1 2 Instruction Endings

3 1 2 1 Completed Instructions

3 1 2 2 Suspended Instructions

3 1 2 3 Terminated Instructions

3 1 2 4 Partially Completed Instructions

3 1 3 Slave Processor Instructions

3 1 3 1 Slave Processor Protocol

3 1 3 2 Floating-Point Instructions

3 2 Exception Processing

3 2 1 Exception Acknowledge Sequence

3 2 2 Returning from an Exception Service

Procedure

3 2 3 Maskable Interrupts

3 2 3 1 Non-Vectored Mode

3 2 3 2 Vectored Mode Non-Cascaded

Case

3 2 3 3 Vectored Mode Cascaded Case

3 2 4 Non-Maskable Interrupt

3 2 5 Traps

3 2 6 Priority among Exceptions

3 2 7 Exception Acknowledge Sequences Detailed

Flow

3 2 7 1 Maskable Non-Maskable Interrupt

Sequence

3 2 7 2 SLAVE ILL SVC DVZ FLG BPT UND

Trap Sequence

3 2 7 3 Trace Trap Sequence

3 3 Debugging Support

3 3 1 Instruction Tracing

3 4 DSP Module

3 4 1 Programming Model

3 4 2 RAM Organization and Data Types

3 4 2 1 Integer Values

3 4 2 2 Aligned-Integer Values

3 4 2 3 Real Values

3 4 3 4 Aligned-Real Values

3 4 2 5 Extended Precision Real Values

3 4 2 6 Complex Values

3 4 3 Command List Format

3 4 4 CPU Core Interface

3 4 4 1 Synchronization of Parallel Operation 42

3 4 4 2 DSPM RAM Organization

3 4 5 DSPM Instruction Set

3 4 5 1 Conventions

3 4 5 2 Type Casting

3 4 5 3 General Notes

3 4 5 4 Load Register Instructions

3 4 5 5 Store Register Instructions

3 4 5 6 Adjust Register Instructions

3 4 5 7 Flow Control Instructions

3 4 5 8 Internal Memory Move Instructions

3 4 5 9 External Memory Move Instructions

3 4 5 10 Arithmetic Logical Instructions

3 4 5 11 Multiply-and-Accumulate

Instructions

3 4 5 12 Multiply-and-Add Instructions

3 4 5 13 Clipping and Min Max Instructions

3 4 5 14 Special Instructions

Table of Contents

(Continued)

3 5 System Interface

3 5 1 Power and Grounding

3 5 2 Clocking

3 5 3 Power Save Mode

3 5 4 Resetting

3 5 5 Bus Cycles

3 5 5 1 Bus Status

3 5 5 2 Basic Read and Write Cycles

3 5 5 3 Cycle Extension

3 5 5 4 Instruction Fetch Cycles

3 5 5 5 Interrupt Control Cycles

3 5 5 6 Special Bus Cycles

3 5 5 7 Slave Processor Bus Cycles

3 5 5 8 Data Access Sequences

3 5 5 9 Bus Access Control

3 5 5 10 Instruction Status

4 0 DEVICE SPECIFICATIONS

4 1 NS32FX164 Pin Descriptions

4 1 1 Supplies

4 1 2 Input Signals

4 1 3 Output Signals

4 1 4 Input-Output Signals

4 2 Absolute Maximum Ratings

4 3 Electrical Characteristics

4 4 Switching Characteristics

4 4 1 Definitions

4 4 2 Timing Tables

4 4 2 1 Output Signals Internal Propagation

Delays

4 4 2 2 Input Signal Requirements

4 4 3 Timing Diagrams

APPENDIX A INSTRUCTION FORMATS

APPENDIX B INSTRUCTION EXECUTION TIMES

B 1 Basic and Floating-Point Instructions

B 1 1 Equations

B 1 2 Notes on Table Use

B 1 3 Calculation of the Execution Time TEX for Basic

Instructions

B 1 4 Calculation of the Execution Time TEX for

Floating-Point Instructions

B 2 Special Graphics Instructions

B 2 1 Execution Time Calculation for Special

Graphics Instructions

B 3 DSPM Instructions

100

List of Figures

FIGURE 1-1

CPU Block Diagram

FIGURE 2-1

NS32FX164 Internal Registers

FIGURE 2-2

Processor Status Register (PSR)

FIGURE 2-3

Configuration Register (CFG)

FIGURE 2-4

DSP Module Registers Address Map

FIGURE 2-5

Accumulator Format

FIGURE 2-6

X Y Z Registers Format

FIGURE 2-7

EABR Register Format

FIGURE 2-8

OVF Register Format

FIGURE 2-9

PARAM Register Format

FIGURE 2-10 REPEAT Register Format

FIGURE 2-11 EXT Register Format

FIGURE 2-12 CLSTAT Register Format

FIGURE 2-13 DSPINT and DSPMASK Register Format

FIGURE 2-14 NMISTAT Register Format

FIGURE 2-15 NS32FX164 Address Mapping

FIGURE 2-16 NS32FX164 Run-Time Environment

FIGURE 2-17 General Instruction Format

FIGURE 2-18 Index Byte Format

FIGURE 2-19 Displacement Encodings

FIGURE 2-20 Correspondence between Linear and Cartesian Addressing

FIGURE 2-21 32-Pixel by 32-Scan Line Frame Buffer

FIGURE 2-22 Overlapping BITBLT Blocks

FIGURE 2-23 BB Instructions Format

FIGURE 2-24 BITWT Instruction Format

FIGURE 2-25 EXTBLT Instruction Format

FIGURE 2-26 MOVMPi Instruction Format

List of Figures

(Continued)

FIGURE 2-27 TBITS Instruction Format

FIGURE 2-28 SBITS Instruction Format

FIGURE 2-29 SBITPS Instruction Format

FIGURE 2-30 Bus Activity for a Simple BITBLT Operation

FIGURE 3-1

Operating States

FIGURE 3-2

Slave Processor Protocol

FIGURE 3-3

Slave Processor Status Word

FIGURE 3-4

Interrupt Dispatch and Cascade Tables

FIGURE 3-5

Exception Acknowledge Sequence Direct-Exception Mode Disabled

FIGURE 3-6

Exception Acknowledge Sequence Direct-Exception Mode Enabled

FIGURE 3-7

Return from Trap (RETTn) Instruction Flow Direct-Exception Mode Disabled

FIGURE 3-8

Return from Interrupt (RETI) Instruction Flow Direct-Exception Mode Disabled

FIGURE 3-9

Interrupt Control Unit Connections (16 Levels)

FIGURE 3-10 Cascaded Interrupt Control Unit Connections

FIGURE 3-11 Exception Processing Flowchart

FIGURE 3-12 Service Sequence

FIGURE 3-13 DSP Module Block Diagram

FIGURE 3-14 Power and Ground Connections

FIGURE 3-15 Crystal Interconnections

30 MHz

FIGURE 3-16 Crystal Interconnections

40 MHz 50 MHz

FIGURE 3-17 Recommended Reset Connections

FIGURE 3-18 Power-On Reset Requirements

FIGURE 3-19 General Reset Timing

FIGURE 3-20 Bus Connections

FIGURE 3-21 Read Cycle Timing

FIGURE 3-22 Write Cycle Timing

FIGURE 3-23 Cycle Extension of a Read Cycle

FIGURE 3-24 Special Bus Cycle Timing

FIGURE 3-25 Slave Processor Read Cycle

FIGURE 3-26 Slave Processor Write Cycle

FIGURE 3-27 NS32FX164 and FPU Interconnections

FIGURE 3-28 Memory Interface

FIGURE 3-29 HOLD Timing (Bus Initially Idle)

FIGURE 3-30 HOLD Timing (Bus Initially Not Idle)

FIGURE 4-1

Connection Diagram

FIGURE 4-2

Output Signals Specification Standard

FIGURE 4-3a Input Signals Specification Standard

FIGURE 4-3b RSTI INT NMI Hysteresis

FIGURE 4-4

Read Cycle

FIGURE 4-5

Write Cycle

FIGURE 4-6

Special Bus Cycle

FIGURE 4-7

HOLD Acknowledge Timing (Bus Initially Not Idle)

FIGURE 4-8

HOLD Timing (Bus Initially Idle)

FIGURE 4-9

External DMA Controller Bus Cycle

FIGURE 4-10 Slave Processor Write Timing

FIGURE 4-11 Slave Processor Read Timing

FIGURE 4-12 SPC Timing

FIGURE 4-13 PFS Signal Timing

FIGURE 4-14 ILO Signal Timing

FIGURE 4-15 Clock Waveforms

FIGURE 4-16 INT Signal Timing

1 0 Product Introduction

The NS32FX164 is a high speed CMOS microprocessor in

the Series 32000 EP family

It includes two main execution units the NS32CG16 com-

patible CPU core and the DSP Module The CPU core is

designed for general purpose computations and system

control functions The DSP Module is tuned to perform the

DSP primitives needed in Voice Band Modems

The

NS32FX164 also incorporates a 4K-byte RAM Array as a

shared resource for both the CPU core and the DSP Module

(2K-byte in the NS32FV16 and the NS32FX161)

The NS32FX164 is software-compatible with all other CPUs

in the family

The device incorporates all of the Series 32000 advanced

architectural features with the exception of the virtual mem-

ory capability

Brief descriptions of the NS32FX164 features that are

shared with other members of the family are provided be-

low

Powerful Addressing Modes

Nine addressing modes

available to all instructions are included to access data

structures efficiently

Data Types

The architecture provides for numerous data

types such as byte word doubleword and BCD which may

be arranged into a wide variety of data structures

Symmetric Instruction Set

While avoiding special case

instructions that compilers can’t use the Series 32000 fami-

ly incorporates powerful instructions for control operations

such as array indexing and external procedure calls which

save considerable space and time for compiled code

Memory-to-Memory Operations

The Series 32000 CPUs

represent two-address machines This means that each op-

erand can be referenced by any one of the addressing

modes provided

This powerful memory-to-memory architecture permits

memory locations to be treated as registers for all useful

operations This is important for temporary operands as well

as for context switching

Large Uniform Addressing

The NS32FX164 has 24-bit

address pointers that can address up to 16 megabytes with-

out any segmentation this addressing scheme provides

flexible memory management without add-on expense

Modular Software Support

Any software package for the

Series 32000 architecture can be developed independent of

all other packages without regard to individual addressing

In addition ROM code is totally relocatable and easy to

access which allows a significant reduction in hardware and

software cost

Software Processor Concept

The Series 32000 architec-

ture allows future expansions of the instruction set that can

be executed by special slave processors acting as exten-

sions to the CPU This concept of slave processors is

unique to the Series 32000 architecture It allows software

compatibility even for future components because the slave

hardware is transparent to the software With future ad-

vances in semiconductor technology the slaves can be

physically integrated on the CPU chip itself

To summarize the architectural features cited above pro-

vide three primary performance advantages and character-

istics

High-Level Language Support

Easy Future Growth Path

Application Flexibility

1 1 NS32FX164 SPECIAL FEATURES

In addition to the above Series 32000 features

the

NS32FX164 provides features that make the device ex-

tremely attractive for a wide range of applications where

graphics support low chip count and low power consump-

tion are required

The most relevant of these features are the enhanced Digi-

tal Signal Processing performance which makes the chip

very attractive for facsimile applications and the graphics

support capabilities that can be used in applications such

as printers CRT terminals and other varieties of display

systems where text and graphics are to be handled

Graphics support is provided by eighteen instructions that

allow operations such as BITBLT data compression expan-

sion fills and line drawing to be performed very efficiently

In addition the device can be easily interfaced to an exter-

nal BITBLT Processing Unit (BPU) for high BITBLT perform-

ance

The NS32FX164 allows systems to be built with a relatively

small amount of random logic The bus is highly optimized

to allow simple interfacing to a large variety of DRAMs and

peripheral devices All the relevant bus access signals and

clock signals are generated on-chip The cycle extension

logic is also incorporated on-chip

The device is fabricated in a low-power high speed CMOS

technology It also includes a power-save feature that al-

lows the clock to be slowed down under software control

thus minimizing the power consumption This feature can be

used in those applications where power saving during peri-

ods of low performance demand is highly desirable

The power save feature the DSP Module and the Bus Char-

acteristics are described in the ‘‘Functional Description’’

section A general overview of BITBLT operations and a

description of the graphics support instructions is provided

in Section 2 5 Details on all the NS32FX164 graphics in-

structions can be found in the NS32CG16 Printer Display

Processor Programmer’s Reference Supplement

1 0 Product Introduction

(Continued)

Below is a summary of the instructions that are directly ap-

plicable to graphics along with their intended use

Instruction

Application

BBAND

The BITBLT group of instructions provide a

BBOR

method of quickly imaging characters

BBFOR

creating patterns windowing and other

BBXOR

block oriented effects

BBSTOD

BITWT

EXTBLT

MOVMP

Move Multiple Pattern is a very fast

instruction for clearing memory and drawing

patterns and lines

TBITS

Test Bit String will measure the length of 1’s

or 0’s in an image supporting many data

compression methods (RLL) TBITS may

also be used to test for boundaries of

images

SBITS

Set Bit String is a very fast instruction for

filling objects outline characters and

drawing horizontal lines

The TBITS and SBITS instructions support

Group 3 and Group 4 CCITT standards for

compression and decompression

algorithms

SBITPS

Set Bit Perpendicular String is a very fast

instruction for drawing vertical horizontal

and 45 lines

In printing applications SBITS and SBITPS

may be used to express portrait and

landscape respectively from the same

compressed font data The size of the

character may be scaled as it is drawn

SBIT

The Bit group of instructions enable single

CBIT

pixels anywhere in memory to be set

TBIT

cleared tested or inverted

IBIT

INDEX

The INDEX instruction combines a multiply-

add sequence into a single instruction This

provides a fast translation of an X-Y

address to a pixel relative address

2 0 Architectural Description

2 1 REGISTER SET

The NS32FX164 has 32 internal registers 17 of these regis-

ters belong to the CPU portion of the device and are ad-

dressed either implicitly by specific instructions or through

the register addressing mode The other 15 control the op-

eration of the DSP Module and are memory mapped

Figure

2-1 shows the NS32FX164 internal registers

CPU Registers

General Purpose

32 Bits

R0 – R7

Address

SP0 SP1

INTBASE

MOD

Processor Status

PSR

Configuration

CFG

Peripherals Registers

DSP Module

EABR

CLPTR

OVF

PARAM

REPEAT

ABORT

EXT

CLSTAT

DSPINT

DSPMASK

NMISTAT

FIGURE 2-1 NS32FX164 Internal Registers

2 1 1 General Purpose Registers

There are eight registers (R0 – R7) used for satisfying the

high speed general storage requirements such as holding

temporary variables and addresses The general purpose

registers are free for any use by the programmer They are

32 bits in length If a general purpose register is specified for

an operand that is 8 or 16 bits long only the low part of the

2 0 Architectural Description

(Continued)

2 1 2 Address Registers

The seven address registers are used by the processor to

implement specific address functions Except for the MOD

description of the address registers follows

Program Counter

The PC register is a pointer to the

first byte of the instruction currently being executed The PC

is used to reference memory in the program section

SP0 SP1

Stack Pointers

The SP0 register points to the

lowest address of the last item stored on the INTERRUPT

STACK This stack is normally used only by the operating

system It is used primarily for storing temporary data and

holding return information for operating system subroutines

and interrupt and trap service routines The SP1 register

points to the lowest address of the last item stored on the

USER STACK This stack is used by normal user programs

to hold temporary data and subroutine return information

When a reference is made to the selected Stack Pointer

(see PSR S-bit) the terms ‘‘SP Register’’ or ‘‘SP’’ are used

SP refers to either SP0 or SP1 depending on the setting of

the S bit in the PSR register If the S bit in the PSR is 0 SP

refers to SP0 If the S bit in the PSR is 1 then SP refers to

SP1

Stacks in the Series 32000 architecture grow downward in

memory A Push operation pre-decrements the Stack Point-

er by the operand length A Pop operation post-increments

the Stack Pointer by the operand length

Frame Pointer

The FP register is used by a procedure

to access parameters and local variables on the stack The

FP register is set up on procedure entry with the ENTER

instruction and restored on procedure termination with the

EXIT instruction

The frame pointer holds the address in memory occupied by

the old contents of the frame pointer

Static Base

The SB register points to the global vari-

ables of a software module This register is used to support

relocatable global variables for software modules The SB

the global variables of a module

INTBASE

Interrupt Base

The INTBASE register holds

the address of the dispatch table for interrupts and traps

(Section 3 2 1)

MOD

Module

The MOD register holds the address of the

module descriptor of the currently executing software mod-

ule The MOD register is 16 bits long therefore the module

table must be contained within the first 64 kbytes of memo-

2 1 3 Processor Status Register

The Processor Status Register (PSR) holds status informa-

tion for the microprocessor

The PSR is sixteen bits long divided into two eight-bit

halves The low order eight bits are accessible to all pro-

grams but the high order eight bits are accessible only to

programs executing in Supervisor Mode

FIGURE 2-2 Processor Status Register (PSR)

The C bit indicates that a carry or borrow occurred after

an addition or subtraction instruction It can be used with

the ADDC and SUBC instructions to perform multiple-

precision integer arithmetic calculations It may have a

setting of 0 (no carry or borrow) or 1 (carry or borrow)

The T bit causes program tracing If this bit is set to 1 a

TRC trap is executed after every instruction (Section

3 3 1)

The L bit is altered by comparison instructions In a com-

parison instruction the L bit is set to ‘‘1’’ if the second

operand is less than the first operand when both oper-

ands are interpreted as unsigned integers Otherwise it

is set to ‘‘0’’ In Floating-Point comparisons this bit is

always cleared

Reserved for use by the CPU

The F bit is a general condition flag which is altered by

many instructions (e g

integer arithmetic instructions

use it to indicate overflow)

The Z bit is altered by comparison instructions In a com-

parison instruction the Z bit is set to ‘‘1’’ if the second

operand is equal to the first operand otherwise it is set

to ‘‘0’’

The N bit is altered by comparison instructions In a

comparison instruction the N bit is set to ‘‘1’’ if the sec-

ond operand is less than the first operand when both

operands are interpreted as signed integers Otherwise

it is set to ‘‘0’’

If the U bit is ‘‘1’’ no privileged instructions may be exe-

cuted If the U bit is ‘‘0’’ then all instructions may be

executed When U

0 the processor is said to be in Su-

pervisor Mode when U

1 the processor is said to be in

User Mode A User Mode program is restricted from exe-

cuting certain instructions and accessing certain regis-

ters which could interfere with the operating system For

example

a User Mode program is prevented from

changing the setting of the flag used to indicate its own

privilege mode A Supervisor Mode program is assumed

to be a trusted part of the operating system hence it has

no such restrictions

The S bit specifies whether the SP0 register or SP1 reg-

ister is used as the Stack Pointer The bit is automatical-

ly cleared on interrupts and traps It may have a setting

of 0 (use the SP0 register) or 1 (use the SP1 register)

The P bit prevents a TRC trap from occurring more than

once for an instruction (Section 3 3 1) It may have a

setting of 0 (no trace pending) or 1 (trace pending)

If I

1 then all interrupts will be accepted If I

0 only

the NMI interrupt is accepted Trap enables are not af-

fected by this bit

2 0 Architectural Description

(Continued)

Reserved for use by the CPU This bit is set to 1 during

the execution of the EXTBLT instruction and causes the

BPU signal to become active Upon reset B is set to

zero and the BPU signal is set high

Note 1

When an interrupt is acknowledged the B I P S and U bits are set

to zero and the BPU signal is set high A return from interrupt will

restore the original values from the copy of the PSR register saved

in the interrupt stack

Note 2

If BITBLT (BB) or EXTBLT instructions are executed in an interrupt

routine the PSR bits J and K must be cleared first

2 1 4 Configuration Register

The Configuration Register (CFG) is 32 bits wide of which 5

bits are implemented The implemented bits enable various

operating modes for the CPU including vectoring of inter-

rupts execution of floating-point instructions processing of

exceptions and selection of clock scaling factor The CFG is

programmed by the SETCFG instruction The format of CFG

is shown in

Figure 2-3 The various control bits are de-

scribed below

Reserved

Res

C M F

FIGURE 2-3 Configuration Register (CFG)

Interrupt vectoring This bit controls whether maskable

interrupts are handled in nonvectored (I

0) or vec-

tored (I

1) mode Refer to Section 3 2 3 for more in-

formation

Floating-point instruction set This bit indicates wheth-

er a floating-point unit (FPU) is present to execute

floating-point instructions If this bit is 0 when the CPU

executes a floating-point instruction a Trap (UND) oc-

curs If this bit is 1 then the CPU transfers the instruc-

tion and any necessary operands to the FPU using the

slave-processor protocol described in Section 3 1 3 1

Clock scaling This bit is used in conjunction with the

C-bit to select the clock scaling factor

Clock scaling Same as the M-bit above Refer to Sec-

tion 3 5 3 on ‘‘Power Save Mode’’ for details

Direct-Exception mode enable This bit enables the Di-

rect-Exception mode for processing exceptions When

this mode is selected the CPU response time to inter-

rupts and other exceptions is significantly improved

Refer to Section 3 2 for more information

2 1 5 DSP Module Registers

The DSP Module (DSPM) contains 15 memory-mapped reg-

isters All the registers except OVF CLSTAT ABORT

DSPINT and NMISTAT are readable and writable OVF

CLSTAT DSPINT and NMISTAT are read-only ABORT is

write-only

The DSPM registers are divided into two groups according

to their function PARAM OVF X Y Z A REPEAT CLPTR

and EABR are called DSPM dedicated registers CLSTAT

ABORT DSPINT DSPMASK EXT and NMISTAT are called

CPU core interface registers

Accesses to these registers must be aligned word and dou-

ble-word accesses must occur on word and double-word

address boundaries respectively Failing to do so will cause

unpredictable results

Figure 2-4 shows the address map of

the DSP Module registers

Name

Address

PARAM

FFFF8000

OVF

FFFF8004

FFFF8008